Alpha-induced multiple cell upsets in standard and radiation hardened SRAMs manufactured in a 65 nm CMOS technology

IEEE Transactions on Nuclear Science

Volumn 53, Issue 6, 2006, Pages 3479-3486

  Gasiot, G ^a   Giot, D ^a   Roche, P ^a  

^a STMICROELECTRONICS   (France)

Author keywords

Alpha experiments; CMOS 65 nm; Full 3 D device simulation; Multiple cell upset; Robust SRAM; Soft error rate

Indexed keywords

BIT ERROR RATE; COMPUTER SIMULATION; RADIATION HARDENING; ROBUSTNESS (CONTROL SYSTEMS); STATIC RANDOM ACCESS STORAGE;

ALPHA EXPERIMENTS; CMOS 65 NM; MULTIPLE CELL UPSET; MULTIPLE CELL UPSETS (MCU); ROBUST SRAM;

CMOS INTEGRATED CIRCUITS;

EID: 33846310741     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2006.885007     Document Type: Conference Paper

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