Through silicon via copper electrodeposition for 3D integration

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2008, Pages 577-583

  Beica, Rozalia ^a   Sharbono, Charles ^a   Ritzdorf, Tom ^a  

^a Semitool Incorporated   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; COMPUTER NETWORKS; COPPER; ELECTRIC CONDUCTIVITY; ELECTRONIC EQUIPMENT MANUFACTURE; METALLIZING; OPTICAL INTERCONNECTS; OPTIMIZATION; PACKAGING; PROCESS DESIGN; PROCESS ENGINEERING; SEMICONDUCTING SILICON; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICES; SEMICONDUCTOR MATERIALS; SILICON; SILICON WAFERS; THREE DIMENSIONAL;

COPPER ELECTRODEPOSITION; SEMICONDUCTOR INDUSTRIES; THROUGH SILICON VIA;

ELECTRONICS PACKAGING;

EID: 51349090206     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2008.4550031     Document Type: Conference Paper

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