Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2001, Pages 195-198

  Banerjee, K ^a   Mehrotra, A ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC RESISTANCE; INDUCTANCE; LARGE SCALE SYSTEMS; TELECOMMUNICATION REPEATERS; TIME DOMAIN ANALYSIS; TRANSFER FUNCTIONS;

ON-CHIP INDUCTANCES;

CHIP SCALE PACKAGES;

EID: 0034790238     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. An analytical delay model for RLC interconnects
2. A new analytical delay and noise model for on-chip RLC interconnect
3. Compact distributed RLC models for multilevel interconnect networks
4. Compact distributed RLC models for multilevel interconnect networks
5. Compact distributed RLC interconnect models-Part I. Single line transient, time delay, and overshoot expressions
6. Compact distributed RLC interconnect models-Part II. Coupled line transient expressions and peak crosatalk in multilevel networks
7. Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
8. FASTCAP: A multipole-accelerated 3-D capacitance extraction program