Interconnect performance modeling for 3d integrated circuits with multiple Si layers

Proceedings of the IEEE 1999 International Interconnect Technology Conference, IITC 1999

Volumn , Issue , 1999, Pages 24-26

  Souri, Shukri J ^a   Saraswat, Krishna C ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; THREE DIMENSIONAL INTEGRATED CIRCUITS; TIMING CIRCUITS;

3-D INTEGRATION; CHIP PERFORMANCE; CHIP SIZES; INTERCONNECT PERFORMANCE; LONG INTERCONNECT; MULTIPLE LAYERS; PACKING DENSITY; QUANTITATIVE APPROACH;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 33646125223     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.1999.787067     Document Type: Conference Paper

References (3)

1. B. S. Landman, and R. L. Russo, "On a Pin Versus Block Relationship For Partitions of Logic Graphs," IEEE Trans. Computers, vol. C-20, no. 12, Dec. 1971.
2. A. L. Robinson, L. A. Glasser, and D. A. Antoniadis, "A Simple Interconnect Delay Model For Multilayer Integrated Circuits," IEEE V-MIC Conf. June 9-10, 1986.
3. J. A. Davis, V. K. De, and J.D. Meindl, "A Stochastic Wire-Length Distribution for Gigascale Integration (GSI) - Part II: Applications to Clock Frequency, Power Dissipation, and Chip Size Estimation," IEEE Trans. Elect. Dev. Vol. 45, no. 3, March 1998.