Novel 3-D structures

IEEE International SOI Conference

Volumn , Issue , 1999, Pages 54-55

  Saraswat, K C ^a   Souri, S J ^a   Subramanian, V ^a   Joshi, A R ^a   Wang, A W ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; SEMICONDUCTOR DEVICE MODELS; SILICON WAFERS; SUBSTRATES;

INTERCONNECT DELAYS; MULTIPLE ACTIVE SILICON LAYERS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0033347794     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)