Neuromorphic vision chip fabricated using three-dimensional integration technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 270-271+454

  Koyanagi, M ^a   Nakagawa, Y ^a   Lee, K W ^a   Nakamura, T ^a   Yamada, Y ^a   Inamura, K ^a   Park, K T ^a   Kurino, H ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA PROCESSING; IMAGE PROCESSING; PARALLEL PROCESSING SYSTEMS; PATTERN RECOGNITION; SILICON ON INSULATOR TECHNOLOGY;

NEUROMORPHIC VISION CHIP;

MICROPROCESSOR CHIPS;

EID: 0035054823     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. Intelligent image sensor chip with three dimensional structure
2. Three-dimensional shared memory fabricated using wafer stacking technology