Performance modeling of the interconnect structure of a three-dimensional integrated RISC processor/cache system

IEEE Transactions on Components Packaging and Manufacturing Technology Part B

Volumn 19, Issue 4, 1996, Pages 719-727

  Kühn, Stefan A ^a   Kleiner, Michael B ^a   Ramm, Peter ^b   Weber, Werner ^a  

^a SIEMENS AG   (Germany)

^b Fraunhofer Institut fur Festkorpertechnologie   (Germany)

Author keywords

3 D packaging; 3 D technology; Interconnect; Performance modeling; RISC; Vertically integrated circuits

Indexed keywords

BUFFER STORAGE; CAPACITANCE; COMPUTER SIMULATION; ELECTRONICS PACKAGING; HIERARCHICAL SYSTEMS; MULTICHIP MODULES; PRINTED CIRCUIT BOARDS; PROGRAM PROCESSORS; THREE DIMENSIONAL;

MEMORY HIERARCHY; THREE DIMENSIONAL INTEGRATED CIRCUITS;

REDUCED INSTRUCTION SET COMPUTING;

EID: 0030290949     PISSN: 10709894     EISSN: None     Source Type: Journal    
DOI: 10.1109/96.544362     Document Type: Article

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