Multiple Si layers ICs: motivation, performance analysis, and design implications

Proceedings - Design Automation Conference

Volumn , Issue , 2000, Pages 213-220

  Souri, Shukri J ^a   Banerjee, Kaustav ^a   Mehrota, Amit ^a   Saraswat, Krishna C ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; HEAT SINKS; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; LOGIC CIRCUITS; MULTILAYERS; SEMICONDUCTING SILICON; THERMAL EFFECTS; THREE DIMENSIONAL;

CHIP AREA; INTERCONNECT DELAYS; INTERCONNECT TIERS; VERTICAL INTER LAYER INTERCONNECTS;

VLSI CIRCUITS;

EID: 0033699518     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (71)