Technology for advanced high-performance microprocessors

IEEE Transactions on Electron Devices

Volumn 45, Issue 3, 1998, Pages 620-625

  Bohr, Mark T ^a   El Mansy, Youssef A ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; CMOS INTEGRATED CIRCUITS; MOSFET DEVICES; RANDOM ACCESS STORAGE; SEMICONDUCTOR DEVICE MANUFACTURE;

INTERCONNECT DENSITY;

MICROPROCESSOR CHIPS;

EID: 0032028642     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.661223     Document Type: Article

References (7)

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2. M. Bohr, S. S. Ahmed, S. U. Ahmed, M. Bost, T. Ghani, J. Greason, R. Hainsey, C. Jan, P. Packan, S. Sivakumar, S. Thompson, J. Tsai, and S. Yang, "A high-performance Q.25-/j,m logic technology optimized for 1.8 V operation," in IEDM Tech. Dig., 1996, pp. 847-850.
3. A. Bryant W. Mansch, and T. Mii, "Characteristics of CMOS device isolation for the ULSI age," in IEDM Tech. Dig., 1994, pp. 671-674.
4. S. Thompson, I. Young, J. Greason, and M. Bohr, "Dual threshold voltages and substrate bias: Keys to high-performance, low-power, 0.1ftm logic designs," in Symp. VLSI Technol. Dig., 1997, pp. 69-70.
5. M. Bohr, "MOS transistors: scaling and performance trends,"Semiconduct. Int., vol. 18, no. 6, pp. 75-80, 1995.
6. _, "Interconnect scaling-The real limiter to high-performance ULSI," in IEDM Tech. Dig., 1995, pp. 241-244.
7. J. Greason, D. Buehler, J. Kolousek, Y.-G. Ng, K. Sarkez, P. Shay, and A. Waizman, "A 4.5 megabit, 560 MHz, 4.5 Gbytes/s high bandwidth SRAM," in Symp. VLSI Circuits Dig., 1997, pp. 15-16.