Performance improvement of the memory hierarchy of RISC-systems by application of 3-D technology

IEEE Transactions on Components Packaging and Manufacturing Technology Part B

Volumn 19, Issue 4, 1996, Pages 709-718

  Kleiner, Michael B ^a   Kühn, Stefan A ^a   Ramm, Peter ^b   Weber, Werner ^a  

^a Kraft Jacobs Suchard R and D Inc   (Germany)

^b Fraunhofer Institut fur Festkorpertechnologie   (Germany)

Author keywords

3 D IC; 3 D packaging; 3 D technology; Cache; Memory hierarchy; Modeling; Performance; RISC; Vertically integrated circuits

Indexed keywords

DATA STORAGE EQUIPMENT; ELECTRONICS PACKAGING; HIERARCHICAL SYSTEMS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; PROGRAM PROCESSORS; REDUCED INSTRUCTION SET COMPUTING; THREE DIMENSIONAL;

MEMORY HIERARCHY;

BUFFER STORAGE;

EID: 0030291023     PISSN: 10709894     EISSN: None     Source Type: Journal    
DOI: 10.1109/96.544361     Document Type: Article

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