Architecture and performance of 3-dimensional SOI circuits

IEEE International SOI Conference

Volumn , Issue , 1999, Pages 44-45

  Zhang, Rongtian ^a   Roy, Kaushik ^a   Janes, David B ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER AIDED NETWORK ANALYSIS; COSTS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; MULTIPLYING CIRCUITS; VLSI CIRCUITS;

ARRAY MULTIPLIERS; INTERCONNECTION LAYERS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0033324550     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)