The Effect of Interconnect Scaling and Low-k Dielectric on the Thermal Characteristics of the IC Metal

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 65-68

  Banerjee, Kaustav ^a   Amerasekera, Ajith ^b   Dixit, Girish ^b   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT INTERCONNECTS; TIMING CIRCUITS; CRITICAL CURRENT DENSITY (SUPERCONDUCTIVITY); DIELECTRIC MATERIALS; ELECTRIC IMPEDANCE; INTERCONNECTION NETWORKS; METALS; THERMODYNAMIC PROPERTIES;

CONDITION; DC CONDITIONS; INTERCONNECT STRUCTURES; LOW- K DIELECTRICS; METAL LINE; PULSED CONDITIONS; PULSED CURRENTS; SCALINGS; THERMAL CHARACTERISTICS; THERMAL IMPEDANCE;

LOW-K DIELECTRIC; INTEGRATED CIRCUIT MANUFACTURE;

INTERCONNECT SCALING; INTERCONNECT STRUCTURES; PULSED CURRENT; THERMAL IMPEDANCE;

EID: 0030409383     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.553123     Document Type: Conference Paper

References (8)

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4. W. R. Hunter, "The Implications of Self-Consistent Current Density Design Guidelines Comprehending Electromigration and Joule Heating for Interconnect Technology Evolution", Tech. Dig. IEDM, pp. 483-486, 1995.
5. S. Ramaswamy et al, "EOS/ESD Reliability of Deep Sub-Micron NMOS Protection Devices", Proc. IRPS, pp. 284-291, 1995.
6. K. Banerjee et al, "Characterization of VLSI Circuit Interconnect Heating and Failure under ESD Conditions", Proc. IRPS, pp. 237-245, 1996.
7. B. Zhao et al, "Reliability and Electrical Performance of New Low Dielectric Constant Interlevel Dielectrics for High Performance ULSI Interconnect", Proc. IRPS, pp. 156-163, 1996.
8. T. J. Maloney et al, Transmission line pulsing techniques for circuit modeling of ESD phenomena", ESD/EOSSymp. Proc, pp. 49-54,1985.