Three-dimensional shared memory fabricated using wafer stacking technology

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2000, Pages 165-167

  Lee, K W ^a   Nakamura, T ^a   Ono, T ^a   Yamada, Y ^a   Mizukusa, T ^a   Hashimoto, H ^a   Park, K T ^a   Kurino, H ^a   Koyanagi, M ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; CELLULAR ARRAYS; CHEMICAL VAPOR DEPOSITION; ETCHING; INDUCTIVELY COUPLED PLASMA; LSI CIRCUITS; MOSFET DEVICES; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS;

WAFER STACKING TECHNOLOGY;

PARALLEL PROCESSING SYSTEMS;

EID: 0034453365     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)