Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 798-803

  Banerjee, Kaustav ^a   Mehrotra, Amit ^b  

^a Stanford University   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTATIONAL METHODS; INDUCTANCE; LARGE SCALE SYSTEMS; LOGIC CIRCUITS; OPTIMIZATION;

ON-CHIP INDUCTANCE;

CHIP SCALE PACKAGES;

EID: 0034852695     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2001.156246     Document Type: Article

References (28)

1. 3) and their impact upon large chip performance
2. Frequancy-dependent crosstalk simulation for on-chip interconnectinns
3. Full copper wiring in a sub-0.25 μm CMOS ULSI technology
4. eff CMOS technology with copper interconnects
5. When are transmission-line effects important for on-chip interconnections?
6. The transient response of damped linear networks
7. Inductance calculations in a complex integrated circuit environment
8. A simplified means for computation of interconnect distributed capacitances and inductances
9. FASTHENRY: A multipole-accelerated 3-D inductance extraction program
10. Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis
11. Layout techniques for minimizing on-chip interconnect self-inductance
12. IC analyses including extracted inductance models
13. On-chip inductance issues in multiconductor systems
14. Clocktree RLC extraction with efficient inductance modeling
15. Line inductance extraction and modeling in a real chip with power grid
16. On-chip inductance modeling of VLSI interconnects
17. On-chip inductance modeling and analysis
18. Quick on-chip self- and mutual-inductance screen
19. Dealing with inductance in high-speed chip design
20. Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
21. Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
22. An analytical delay model for RLC interconnects
23. FASTCAP: A multipole-accelerated 3-D capacitance extraction program
24. MOSFET scaling in the next decade and beyond
25. Gate oxide sealing limits and projection
26. On thermal effects in deep sub-micron VLSI interconnects