Impact of line-edge roughness on double-gate Schottky-barrier field-effect transistors

IEEE Transactions on Electron Devices

Volumn 56, Issue 6, 2009, Pages 1211-1219

  Yu, Shimeng ^a   Zhao, Yuning ^a   Zeng, Lang ^a   Du, Gang ^a   Kang, Jinfeng ^a   Han, Ruqi ^a   Liu, Xiaoyan ^a  

^a PEKING UNIVERSITY   (China)

Author keywords

FinFETs; Line edge roughness (LER); Parameter fluctuations; Process variations; Schottky barrier field effect transistors (SBFETs); SRAM stability

Indexed keywords

FINFETS; LINE-EDGE ROUGHNESS (LER); PARAMETER FLUCTUATIONS; PROCESS VARIATIONS; SCHOTTKY-BARRIER FIELD-EFFECT TRANSISTORS (SBFETS); SRAM STABILITY;

FOURIER ANALYSIS; GALERKIN METHODS; POWER SPECTRUM; REGRESSION ANALYSIS; ROUGHNESS MEASUREMENT; SEMICONDUCTING SILICON COMPOUNDS; STATIC RANDOM ACCESS STORAGE;

FIELD EFFECT TRANSISTORS;

EID: 67349233161     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2017644     Document Type: Article

References (50)

1. A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva, "Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1837-1852, Sep. 2003.
2. P. A. Stolk and D. B. M. Klaassen, "The effect of statistical dopant fluctuations on MOS device performance," in IEDM Tech. Dig., 1996, pp. 627-630.
3. P. Oldiges, Q. Lin, K. Petrillo, M. Sanchez, M. Ieong, and M. Hargrove, "Modeling line edge roughness effects in sub 100 nm gate length devices," in Proc. SISPAD, 2000, pp. 131-134.
4. A. Asenov, S. Kaya, and J. H. Davies, "Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations," IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 112-119, Jan. 2002.
5. J. A. Croon, G. Storms, S. Winkelmeier, I. Pollentier, M. Ercken, S. Decoutere, W. Sansen, and H. E. Maes, "Line edge roughness: Characterization, modeling and impact on device behavior," in IEDM Tech. Dig., 2002, pp. 307-310.
6. S. Xiong and J. Bokor, "A simulation study of gate line edge roughness effects on doping profiles of short-channel MOSFET devices," IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 228-232, Feb. 2004.
7. T. Linton, M. Chandhok, B. J. Rice, and G. Schrom, "Determination of the line edge roughness specification for 34 nm devices," in IEDM Tech. Dig., 2002, pp. 303-306.
8. A. J. Bhavnagarwala, X. Tang, and J. D. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 658-665, Apr. 2001.
9. E. Grossar, M. Stucchi, K. Maex, and W. Dehaene, "Read stability and write-ability analysis of SRAM cells for nanometer technologies," IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2577-2588, Nov. 2006.
10. E. J. Nowak, B. A. Rainey, D. M. Fried, J. Kedzierski, M. Ieong, W. Leipold, J. Wright, and M. Breitwisch, "A functional FinFET-DGCMOS SRAM cell," in IEDM Tech. Dig., 2002, pp. 411-414.
11. X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Sub-50 nm FinFET: PMOS," in IEDM Tech. Dig. 1999, pp. 67-70.
12. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig., 2002, pp. 251-254.
13. J. Kedzierski, M. Ieong, E. Nowak, T. S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D. Fried, and H.-S. P.Wong, "Extension and source/drain design for high-performance FinFET devices," IEEE Trans. Electron Devices vol. 50, no. 4, pp. 952-958, Apr. 2003.
14. A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, and K. D. Meyer, "Analysis of the parasitic S/D resistance in multiple-gate FETs," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1132-1140, Jun. 2005.
15. R. T. P. Lee, A. E.-J. Lim, K.-M. Tan, T.-Y. Liow, G.-Q. Lo, G. S. Samudra, D. Z. Chi, and Y.-C. Yeo, "N-channel FinFETs with 25-nm gate length and Schottky-barrier source and drain featuring ytterbium silicide," IEEE Electron Device Lett., vol. 28, no. 2, pp. 164-167, Feb. 2007.
16. H.-C. Lin, M.-F. Wang, F.-J. Hou, H.-N. Lin, C.-Y. Lu, J.-T. Liu, and T.-Y. Huang, "High-performance p-channel Schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions," IEEE Electron Device Lett., vol. 24, no. 2, pp. 102-104, Feb. 2003.
17. J. M. Larson and J. P. Snyder, "Overview and status of metal S/D Schottky-barrier MOSFET technology," IEEE Trans. Electron Devices vol. 53, no. 5, pp. 1048-1058, Jun. 2006.
18. J. Guo and M. Lundstrom, "A computational study of thin-body, double-gate, Schottky barrier MOSFETs," IEEE Trans. Electron Devices vol. 49, no. 11, pp. 1897-1902, Nov. 2002.
19. S. Zhu, J. Chen,M.-F. Li, S. J. Lee, J. Singh, C. X. Zhu, A. Du, C. H. Tung, A. Chin, and D. L. Kwong, "N-type Schottky barrier S/D MOSFET using ytterbium silicide," IEEE Electron Device Lett., vol. 25, no. 8, pp. 565-567, Aug. 2004.
20. G. Larrieu and E. Dubois, "Integration of PtSi-based Schottky-barrier p-MOSFETs with amidgap tungsten gate," IEEE Trans. Electron Devices vol. 52, no. 12, pp. 2720-2726, Dec. 2005.
21. J. Knoch and J. Appenzeller, "Impact of the channel thickness on the performance of Schottky barrier metal-on-semiconductor field-effect transistors," Appl. Phys. Lett., vol. 81, no. 16, pp. 3082-3084, Oct. 2002.
22. A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, and J. Koga, "Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier eight engineering with dopant segregation technique," in VLSI Symp. Tech. Dig., 2004, pp. 168-169.
23. M. Zhang, J. Knoch, Q. T. Zhao, S. Lenk, U. Breuer, and S. Mantl, "Schottky barrier height modulation using dopant segregation in Schottky barrier SOI MOSFETs," in Proc. ESSDERC, 2005, pp. 457-460.
24. M. Zhang, J. Knoch, S.-L. Zhang, S. Feste, M. Schroter, and S. Mantl, "Threshold voltage variation in SOI Schottky-barrier MOSFETs," IEEE Trans. Electron Devices, vol. 55, no. 3, pp. 858-865, Mar. 2008.
25. Y.-K. Choi, L. Chang, P. Ranade, J.-S. Lee, D. Ha, S. Balasubramanian, A. Agarwal, M. Ameen, T.-J. King, and J. Bokor, "FinFET process refinements for improved mobility and gate work function engineering," in IEDM Tech. Dig., 2002, pp. 259-262.
26. G. Roy, A. R. Brown, F. Adamu-Lema, S. Roy, and A. Asenov, "Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs," IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3063-3070, Dec. 2006.
27. A. Asenov, S. Kaya, and A. R. Brown, "Intrinsic parameter fluctuations in decananometer MOSFETs induced by gate line edge roughness," IEEE Trans. Electron Devices, vol. 50, no. 5, pp. 1254-1260, May 2003.
28. E. Baravelli, M. Jurczak, N. Speciale, K. D. Meyer, and A. Dixit, "Impact of LER and random dopant fluctuations on FinFET matching performance," IEEE Trans. Nanotechnol., vol. 7, no. 3, pp. 291-298, May 2008.
29. S. Y. Zhu, H. Y. Yu, S. J. Whang, J. H. Chen, C. Shen, C. Zhu, S. J. Lee, M. F. Li, D. S. H. Chan, W. J. Yoo, A. Du, C. H. Tung, J. Singh, A. Chin, and D. L. Kwong, "Schottky barrier source/drain MOSFETs with high-k gate dielectrics and metal gate electrode," IEEE Electron Device Lett., vol. 25, no. 5, pp. 268-270, May 2004.
30. User's Manual for DESSIS, ISE TCAD Release 10.0, ISE Integr. Syst. Eng. AG, Zürich, Switzerland, 2004.
31. R. A. Vega, "Comparison study of tunneling models for Schottky field effect transistors and the effect of Schottky barrier lowering," IEEE Trans. Electron Devices, vol. 53, no. 7, pp. 1593-1600, Jul. 2006.
32. R. A. Vega and T.-J. King Liu, "A comparative study of dopant-segregated Schottky and raised source/drain double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2665-2677, Oct. 2008.
33. S. Yu, Y. Zhao, Y. C. Song, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, "Full 3-D simulation of gate line edge roughness impact on sub-30 nm FinFETs," in SNW, 2008. Session P1-10.
34. E. Baravelli, A. Dixit, R. Rooyackers, M. Jurczak, N. Speciale, and K. D. Meyer, "Impact of line-edge roughness on FinFET matching performance," IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2466-2474, Sep. 2007.
35. A. Dixit, K. G. Anil, E. Baravelli, P. Roussel, A. Mercha, C. Gustin, M. Bamal, E. Grossar, R. Rooyackers, E. Augendre, M. Jurczak, S. Biesemans, and K. D. Meyer, "Impact of stochastic mismatch on measured SRAM performance of FinFETs with resist/spacer-defined fins: Role of line-edge-roughness," in IEDM Tech. Dig., 2006, pp. 709-712.
36. S. Xiong, T.-J. King, and J. Bokor, "A comparison study of symmetric ultrathin-body double-gate devices with metal S/D and doped S/D," IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1859-1867, Aug. 2005.
37. S. Yu, Y. Zhao, Y. C. Song, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, "3-D simulation of geometrical variations impact on nanoscale FinFETs," in Proc. ICSICT, 2008, pp. 408-411.
38. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proc. IEEE, vol. 89, no. 3, pp. 259-288, Mar. 2001.
39. M. Jang, Y. Kim, J. Shin, S. Lee, and K. Park, "A 50-nm-gate-length erbium-silicided n-type Schottky barrier metal - oxide - semiconductor field-effect transistor," Appl. Phys. Lett., vol. 84, no. 5, pp. 741-743, Feb. 2004.
40. S. Yu, Y. Zhao, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, "Triple-gate FinFETs with fin-thickness optimization to reduce the impact of fin line edge roughness," in Proc. Int. Conf. SSDM, 2008, pp. 440-441.
41. A. Kranti and G. Armstrong, "Performance assessment of nanoscale double- and triple-gate FinFETs," Semicond. Sci. Technol., vol. 21, no. 2, pp. 409-421, Feb. 2006.
42. Y. Zhao, G. Du, J. F. Kang, X. Y. Liu, and R. Q. Han, "An analytical 2D current model of double-gate Schottky-barrier MOSFETs," in Proc. SISPAD, 2008, pp. 133-136.
43. E. Seevinck, F. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol. SSC-22, no. 5, pp. 748-754, Oct. 1987.
44. S. Yu, Y. Zhao, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, "Impact of stochastic mismatch on FinFETs SRAM induced by process variation," in Int. Conf. EDSSC, 2008, pp. 1-4. 4A-3.
45. D. Lekshmanan, A. Bansal, and K. Roy, "FinFET SRAM: Optimizing silicon fin thickness and fin ratio to improve stability at iso area," in Proc. CICC, 2007, pp. 623-626.
46. P. A. Stolk, H. P. Tuinhout, R. Duffy, E. Augendre, L. P. Bellefroid, M. J. B. Bolt, J. Croon, C. J. J. Dachs, F. R. J. Huisman, A. J. Moonen, Y. V. Ponomarev, R. F. M. Roes, M. Da Rold, E. Seevinck, K. N. Sreerambhatla, R. Surdeanu, R. M. D. A. Velghe, M. Vertregt, M. N. Webster, N. K. J. van Winkelhoff, and A. T. A. Zegers-Van Duijnhoven, "CMOS device optimization for mixed-signal technologies," in IEDM Tech. Dig., 2001, pp. 215-218.
47. S. Yu, Y. Zhao, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, "The impact of line edge roughness on the stability of a FinFET SRAM," Semicond. Sci. Technol., vol. 24, no. 2, p. 025 005, Feb. 2009.
48. B. Cheng, S. Roy, G. Roy, A. Brown, and A. Asenov, "Impact of random dopant fluctuation on bulk CMOS 6-T SRAM scaling," in ESSDERC, 2006, pp. 258-261.
49. L. Chang, D. M. Fried, J. Hergenrother, J. W. Sleight, R. H. Dennard, R. K. Montoye, L. Sekaric, S. J. McNab, A. W. Topol, C. D. Adams, K. W. Guarini, and W. Haensch, "Stable SRAM cell design for the 32 nm node and beyond," in VLSI Symp. Tech. Dig., 2005, pp. 128-129.
50. L. Chang, R. K. Montoye, Y. Nakamura, K. A. Batson, R. J. Eickemeyer, R. H. Dennard, W. Haensch, and D. Jamsek, "An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 956-963, Apr. 2008.