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IEEE Transactions on Electron Devices

Volumn 51, Issue 2, 2004, Pages 228-232

A simulation study of gate line edge roughness effects on doping profiles of short-channel MOSFET devices

(2) Xiong, Shiying a Bokor, Jeffrey a

a UNIVERSITY OF CALIFORNIA (United States)

Author keywords

Doping profiles; Gate line edge roughness (LER); MOSFET; Simulation

Indexed keywords

CALCULATIONS; COMPUTER SIMULATION; DIFFUSION; GATES (TRANSISTOR); ION IMPLANTATION; LOW PASS FILTERS; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; SURFACE ROUGHNESS;

GATE LINE EDGE ROUGHNESS; IMPLANTATION SCATTERING; ROUGHNESS TRANSFER; THERMAL BUDGET;

MOSFET DEVICES;

EID: 0442326805 PISSN: 00189383 EISSN: None Source Type: Journal
DOI: 10.1109/TED.2003.821563 Document Type: Article

Times cited : (65)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.