N-channel FinFETs with 25-nm gate length and Schottky-Barrier source and drain featuring Ytterbium silicide

IEEE Electron Device Letters

Volumn 28, Issue 2, 2007, Pages 164-167

  Lee, Rinus T P ^a   Lim, Andy Eu Jin ^a   Tan, Kian Ming ^a   Liow, Tsung Yang ^a   Lo, Guo Qiang ^b   Samudra, Ganesh S ^a   Chi, Dong Zhi ^c   Yeo, Yee Chia ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

^c INSTITUTE OF MATERIALS RESEARCH AND ENGINEERING   (Singapore)

Author keywords

FinFET; Multiple gate transistor; Rare earth metal; Schottky; Silicide YbSi

Indexed keywords

DRAIN CURRENT; MESFET DEVICES; SCHOTTKY BARRIER DIODES; SILICIDES; YTTERBIUM COMPOUNDS;

MULTIPLE-GATE TRANSISTOR; YTTERBIUM SILICIDE;

CMOS INTEGRATED CIRCUITS;

EID: 33847342014     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.889233     Document Type: Article

References (20)

1. D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takedea, "A fully depleted lean-channel transistor (DELTA) - A novel vertical ultra thin SOI MOSFET," in IEDM Tech. Dig., Dec. 1989, pp. 833-836.
2. Y. K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T. J. King, J. Bokor, and C. Hu, "Sub-20 nm CMOS FinFET technologies," in IEDM Tech. Dig., Dec. 2000, pp. 719-722.
3. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Y. Yang, C. Tabery, C. Ho, Q. Xiang, T. J. King, J. Bokor, C. Hu, M. R. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig., Dec. 2002, pp. 251-254.
4. J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin, D. Lionberger, M. Metz, W. Rachmady, M. Radosavljevic, U. Shah, N. Zelick, and R. Chau, "Tri-gate transistor architecture with high-κ gate dielectrics, metal gates and strain engineering," in VLSI Symp. Tech. Dig., Jun. 2006, pp. 62-63.
5. J. Kedzierski, M. Ieong, E. Nowak, T. S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D. Fried, and H. S. P.Wong, "Extension and source/drain design for high performance FinFET devices," IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 952-958, Apr. 2003.
6. A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, and K. D. Meyer, "Analysis of the parasitic S/D resistance in multiple-gate FETs," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1132-1140, Jun. 2005.
7. D. Connelly, C. Faulkner, and D. E. Grupp, "Performance advantage of Schottky source/drain in ultrathin-body silicon-on-insulator and dual-gate CMOS," IEEE Trans. Electron Devices, vol. 50, no. 5, pp. 1340-1345, May 2003.
8. D. Connelly, C. Faulkner, and D. E. Grupp, "A new route to zero-barrier metal source/drain MOSFETs," IEEE Trans. Nanotechnol., vol. 3, no. 1, pp. 98-104, Mar. 2004.
9. C. H. Ko, H.W. Chen, T. J. Wang, T.M. Kuan, J. W. Hsu, C. Y. Huang, C. H. Ge, L. S. Lai, and W. C. Lee, "NiSi Schottky barrier process-strained Si (SB-PSS) CMOS technology for high performance applications," in VLSI Symp. Tech. Dig., Jun. 2006, pp. 98-99.
10. J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T.-J. King, and C. Hu, "Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime," in IEDM Tech. Dig., Dec. 2000, pp. 57-60.
11. J. M. Larson and J. P. Snyder, "Overview and status of metal S/D Schottky-barrier MOSFET technology," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1048-1058, Jun. 2006.
12. S. Y. Zhu, H. Y. Yu, S. J. Whang, J. H. Chen, C. Shen, C. Zhu, S. J. Lee, M. F. Li, D. S. H. Chan, W. J. Yoo, A. Du, C. H. Tung, J. Singh, A. Chin, and D. L. Kwong, "Schottky barrier source/drain MOSFETs with high-κ gate dielectrics and metal gate electrode," IEEE Electron Device Lett., vol. 25, no. 6, pp. 268-270, 2004.
13. S. Y. Zhu, J. D. Chen, M. F. Li, S. J. Lee, J. Singh, C. X. Zhu, A. Du, C. H. Tung, A. Chin, and D. L. Kwong, "N-type Schottky-barrier source/drain MOSFET using ytterbium silicide," IEEE Electron Device Lett., vol. 25, no. 8, pp. 565-567, Aug. 2004.
14. 2 in contact with thin metal films," Mater. Chem. Phys., vol. 92, no. 2/3, pp. 487-491, Aug. 2005.
15. T.-Y. Liow, K.-M. Tan, R. T. P. Lee, A. Du, C.-H. Tung, G. S. Samudra, W.-J. Yoo, N. Balasubramanian, and Y.-C. Yeo, "Strained n-channel FinFETs with 25 nm gate length and silicon-carbon source/drain regions for performance enhancement," in VLSI Symp. Tech. Dig., Jun. 2006, pp. 68-69.
16. T.-Y. Liow, K.-M. Tan, H.-C. Chin, R. T. P. Lee, C.-H. Tung, G. S. Samudra, N. Balasubramanian, and Y.-C. Yeo, "Carrier transport characteristics of sub-30 nm strained n-channel FinFETs featuring silicon-carbon source/drain regions and methods for further performance enhancement," in IEDM Tech. Dig., Dec. 2006, pp. 473-476.
17. E. H. Rhoderick and R. H. Williams, Metal-Semiconductor Contacts, 2nd ed. Oxford, U.K.: Clarendon, 1998.
18. D. Connelly, C. Faulkner, and D. E. Grupp, "Optimizing Schottky S/D offset for 25-nm dual-gate CMOS performance," IEEE Electron Device Lett., vol. 24, no. 6, pp. 411-413, Jun. 2003.
19. F.-L. Yang, D.-H. Lee, H.-Y. Chen, C.-Y. Chang, S.-D. Liu, C.-C. Huang, T.-X. Chung, H.-W. Chen, C.-C. Huang, Y.-H. Liu, C.-C.Wu, C.-C. Chen, S.-C. Chen, Y.-T. Chen, Y.-H. Chen, C.-J. Chen, B.-W. Chan, P.-F. Hsu, J.-H. Shieh, H.-J. Tao, Y.-C. Yeo, Y. Li, J.-W. Lee, P. Chen, M.-S. Liang, and C. Hu, "5 nm-gate nanowire FinFET," in VLSI Symp. Tech. Dig., Jun. 2004, pp. 196-197.
20. K. G. Anil, P. Verheyen, N. Collaert, A. Dixit, B. Kaczer, J. Snow, R. Vos, S. Locorotondo, B. Degroote, X. Shi, R. Rooyackers, G. Mannaret, S. Brus, Y. S. Yim, A. Lauwers, M. Goodwin, J. A. Kittl, M. V. Dal, O. Richard, A. Veloso, S. Kubicek, W. Boullart, K. De. Meyer, P. Absil, M. Jurczak, and S. Biesemans, "CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and gate using a novel dual hard mask approach," in VLSI Symp. Tech. Dig., Jun. 2005, pp. 198-199.