The impact of line edge roughness on the stability of a FinFET SRAM

Semiconductor Science and Technology

Volumn 24, Issue 2, 2009, Pages

  Yu, Shimeng ^a   Zhao, Yuning ^a   Du, Gang ^a   Kang, Jinfeng ^a   Han, Ruqi ^a   Liu, Xiaoyan ^a  

^a PEKING UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

6T CELLS; 8T CELLS; AUTO CORRELATION FUNCTIONS; FIN-THICKNESS; GATE BIAS VOLTAGES; GAUSSIAN; LINE EDGE ROUGHNESS; MIXED MODES; NANOSCALE CMOS; POSSIBLE SOLUTIONS; READ STABILITIES; ROOT MEAN SQUARES; SCALING TRENDS; STATIC-NOISE MARGINS; SUPPLY VOLTAGES; WRITE OPERATIONS;

ACCESS CONTROL; CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; FIELD EFFECT TRANSISTORS; FINS (HEAT EXCHANGE); FOURIER ANALYSIS; PHOTORESISTS; POWER SPECTRUM; REGRESSION ANALYSIS; STATIC RANDOM ACCESS STORAGE;

ROUGHNESS MEASUREMENT;

EID: 64249107066     PISSN: 02681242     EISSN: 13616641     Source Type: Journal    
DOI: 10.1088/0268-1242/24/2/025005     Document Type: Article

References (30)

1. Frank D J, Dennard R H, Nowak E, Solomon P M, Taur Y and Wong H-S P 2001 Device scaling limits of Si MOSFETs and their application dependencies Proc. IEEE 89 259-88
2. Asenov A, Brown A R, Davies J H, Kaya S and Slavcheva G 2003 Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs IEEE Trans. Electron Devices 50 1837-52
3. Stolk P A and Klaasen D B M 1996 The effect of statistical dopant fluctuations on MOS device performance IEDM Tech. Dig. pp 627-30
4. Oldiges P, Lin Q, Pertillo K, Sanchez M, Ieong M and Hargrove M 2000 Modeling line edge roughness effects in sub 100 nm gate length devices Proc. SISPAD pp 131-4
5. Bhavnagarwala A J, Tang X and Meindl J D 2001 The impact of intrinsic device fluctuations on CMOS SRAM cell stability IEEE J. Solid-State Circuits 36 658-65
6. Grossar E, Stucchi M, Maex K and Dehaene W 2006 Read stability and write-ability analysis of SRAM cells for nanometer technologies IEEE J. Solid-State Circuits 41 2577-88
7. Bhavnagarwala A, Kosonocky S, Radens C, Stawiasz K, Mann R, Ye Q and Chin K 2005 Fluctuation limits and scaling opportunities for CMOS SRAM cells IEDM Tech. Dig. pp 659-62
8. Yu B et al 2002 FinFET scaling to 10 nm gate length IEDM Tech. Dig. pp 251-4
9. Nowak E J, Rainey B A, Fried D M, Kedzierski J, Ieong M, Leipold W, Wright J and Breitwisch M 2002 A functional FinFET-DGCMOS SRAM cell IEDM Tech. Dig. pp 411-4
10. Dixit A et al 2006 Impact of stochastic mismatch on measured SRAM performance of FinFETs with resist/spacer-defined fins: role of line-edge-roughness IEDM Tech. Dig. pp 709-12
11. Inaba S, Kawasaki H, Okano K, Izumida T, Yagishita A, Kaneko A, Ishimaru K, Aoki N and Toyoshima Y 2007 Direct evaluation of DC characteristic variability in FinFET SRAM cell for 32 nm node and beyond IEDM Tech. Dig. pp 487-90
12. Croon J A, Storms G, Winkelmeier S, Pollentier I, Ercken M, Decoutere S, Sansen W and Maes H E 2002 Line edge roughness: characterization, modeling and impact on device behavior IEDM Tech. Dig. pp 307-10
13. Baravelli E, Dixit A, Rooyackers R, Jurczak M, Speciale N and Meyer K D 2007 Impact of line-edge roughness on FinFET matching performance IEEE Trans. Electron Devices 54 2466-74
14. Baravelli E, Jurczak M, Speciale N, Meyer K D and Dixit A 2008 Impact of LER and random dopant fluctuations on FinFET matching performance IEEE Trans. Nanotechnol. 7 291-8
15. Xiong S and Bokor J 2003 Sensitivity of double-gate and FinFET devices to process variations IEEE Trans. Electron Devices 50 2255-61
16. Yu S, Zhao Y N, Song Y C, Du G, Kang J F, Han R Q and Liu X Y 2008 Full 3-D simulation of gate line edge roughness impact on sub-30 nm FinFETs Silicon Nanoelectronics Workshop (SNW) pp 1-10
17. Yu S, Zhao Y N, Song Y C, Du G, Kang J F, Han R Q and Liu X Y 2008 3-D simulation of geometrical variations impact on nanoscale FinFETs Int. Conf. on Solid-State and Integrated Circuits Technology (ICSICT) pp 408-11
18. Lekshmanan D, Bansal A and Roy K 2007 FinFET SRAM: optimizing silicon fin thickness and fin ratio to improve stability at iso area Custom Integrated Circuits Conf. (CICC) pp 623-6
19. Seevinck E, List F and Lohstroh J 1987 Static-noise margin analysis of MOS SRAM cells IEEE J. Solid-State Circuits 22 748-54
20. Rashmi, Kranti A and Armstrong G A 2008 6-T SRAM cell design with nanoscale double-gate SOI MOSFETs impact of source drain engineering and circuit topology Semicond. Sci. Technol. 23 075049
21. ISE-TCAD Tools A package of software in process, device and circuit simulations from Integrated System Engineering (ISE) DESSIS is the tool for multi-dimensional device simulations
22. Stolk P A et al 2001 CMOS device optimization for mixed-signal technologies IEDM Tech. Dig. pp 215-8
23. Bansal A, Mukhopadhyay S and Roy K 2007 Device-optimization technique for robust and low-power FinFET SRAM design in nanoscale era IEEE Trans. Electron Devices 54 1409-19
24. Yu S, Zhao Y N, Du G, Kang J F, Han R Q and Liu X Y 2008 Triple-gate FinFETs with fin-thickness optimization to reduce the impact of fin line edge roughness Int. Conf. on Solid State Devices and Materials (SSDM) pp 440-1
25. Kranti A and Armstrong G 2006 Performance assessment of nanoscaledouble- and triple-gate FinFETs Semicond. Sci. Technol. 21 409-21
26. Collaert N et al 2008 Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10 nm and 30 nm gate length Proc. IEEE ICICDT Conf. pp 59-62
27. Cheng B, Roy S, Roy G, Brown A and Asenov A 2006 Impact of random dopant fluctuation on bulk CMOS 6-T SRAM scaling ESSDERC pp 258-61
28. Chang L et al 2005 Stable SRAM cell design for the 32 nm node and beyond Symp. VLSI Technology Dig. pp 128-9
29. Cheng B, Roy S and Asenov A 2007 The scalability of 8T-SRAM cells under the influence of intrinsic parameter fluctuations ESSDERC pp 93-6
30. Chang L, Montoye R K, Nakamura Y, Batson K A, Eickemeyer R J, Dennard R H, Haensch W and Jamsek D 2008 An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches IEEE J. Solid-State Circuits 43 956-63