-
1
-
-
33745116218
-
A look into the future of nanoelectronics
-
G. Decklerk, "A look into the future of nanoelectronics," in VLSI Symp. Tech. Dig., 2005, pp. 6-7.
-
(2005)
VLSI Symp. Tech. Dig
, pp. 6-7
-
-
Decklerk, G.1
-
2
-
-
84907709834
-
Impact of parametric mismatch and fluctuations on performance and yield of deep-submicron CMOS technologies
-
Florence, Italy
-
H. P. Tuinhout, "Impact of parametric mismatch and fluctuations on performance and yield of deep-submicron CMOS technologies," in Proc. ESSDERC, Florence, Italy, 2002, pp. 95-101.
-
(2002)
Proc. ESSDERC
, pp. 95-101
-
-
Tuinhout, H.P.1
-
3
-
-
14844337078
-
Impact of intrinsic parameter fluctuations in decanano MOSFETs on yield and functionality of SRAM cells
-
May
-
B. Cheng, S. Roy, G. Roy, F. Adamu-Lema, and A. Asenov, "Impact of intrinsic parameter fluctuations in decanano MOSFETs on yield and functionality of SRAM cells," Solid State Electron., vol. 49, no. 5, pp. 740-746, May 2005.
-
(2005)
Solid State Electron
, vol.49
, Issue.5
, pp. 740-746
-
-
Cheng, B.1
Roy, S.2
Roy, G.3
Adamu-Lema, F.4
Asenov, A.5
-
4
-
-
0042912833
-
Simulation of intrinsic parameter fluctuations in decananometre and nanometre scale MOSFETs
-
Sep
-
A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva, "Simulation of intrinsic parameter fluctuations in decananometre and nanometre scale MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1837-1852, Sep. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.9
, pp. 1837-1852
-
-
Asenov, A.1
Brown, A.R.2
Davies, J.H.3
Kaya, S.4
Slavcheva, G.5
-
5
-
-
0016538539
-
Effect of randomness in the distribution of impurity ions on FET thresholds in integrated electronics
-
Aug
-
R. W. Keyes, "Effect of randomness in the distribution of impurity ions on FET thresholds in integrated electronics," IEEE J. Solid-State Circuits, vol. SSC-10, no. 4, pp. 245-247, Aug. 1975.
-
(1975)
IEEE J. Solid-State Circuits
, vol.SSC-10
, Issue.4
, pp. 245-247
-
-
Keyes, R.W.1
-
6
-
-
0028548950
-
Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs
-
Nov
-
T. Mizuno, J. Okamura, and A. Toriumi, "Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs," IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 2216-2221, Nov. 1994.
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, Issue.11
, pp. 2216-2221
-
-
Mizuno, T.1
Okamura, J.2
Toriumi, A.3
-
7
-
-
0022891057
-
Characterisation and modelling of mismatch in MOS transistors for precision analogue design
-
Dec
-
K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, "Characterisation and modelling of mismatch in MOS transistors for precision analogue design," IEEE J. Solid-State Circuits, vol. SSC-21, no. 6, pp. 1057-1066, Dec. 1986.
-
(1986)
IEEE J. Solid-State Circuits
, vol.SSC-21
, Issue.6
, pp. 1057-1066
-
-
Lakshmikumar, K.R.1
Hadaway, R.A.2
Copeland, M.A.3
-
8
-
-
0031646544
-
Matching analysis of deposition defined 50-nm MOSFETs
-
Jan
-
J. T. Horstmann, U. Hilleringmann, and K. F. Goser, "Matching analysis of deposition defined 50-nm MOSFETs," IEEE Trans. Electron Devices, vol. 45, no. 1, pp. 299-306, Jan. 1997.
-
(1997)
IEEE Trans. Electron Devices
, vol.45
, Issue.1
, pp. 299-306
-
-
Horstmann, J.T.1
Hilleringmann, U.2
Goser, K.F.3
-
9
-
-
0030396105
-
The effect of statistical dopant fluctuations on MOS device performance
-
P. A. Stolk and D. B. M. Klaasen, "The effect of statistical dopant fluctuations on MOS device performance," in IEDM Tech. Dig., 1996, pp. 627-630.
-
(1996)
IEDM Tech. Dig
, pp. 627-630
-
-
Stolk, P.A.1
Klaasen, D.B.M.2
-
10
-
-
0035364688
-
An experimentally validated analytical model for gate line edge roughness (LER) effects on technology scaling
-
Jun
-
C. H. Diaz, H.-J. Tao, Y.-C. Ku, A. Yen, and K. Young, "An experimentally validated analytical model for gate line edge roughness (LER) effects on technology scaling," IEEE Electron Device Lett., vol. 22, no. 6, pp. 287-289, Jun. 2001.
-
(2001)
IEEE Electron Device Lett
, vol.22
, Issue.6
, pp. 287-289
-
-
Diaz, C.H.1
Tao, H.-J.2
Ku, Y.-C.3
Yen, A.4
Young, K.5
-
11
-
-
10644264480
-
Experimental investigation of the effect of LWR on sub-100-nm device performance
-
Dec
-
H.-W. Kim, J.-Y. Lee, J. Shin, S.-G. Woo, H.-K. Cho, and J.-T. Moon, "Experimental investigation of the effect of LWR on sub-100-nm device performance," IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 1984-1988, Dec. 2004.
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, Issue.12
, pp. 1984-1988
-
-
Kim, H.-W.1
Lee, J.-Y.2
Shin, J.3
Woo, S.-G.4
Cho, H.-K.5
Moon, J.-T.6
-
12
-
-
33748536476
-
Experimental investigation of the impact of line edge roughness on MOSFET performance and yield
-
J. A. Groon, L. H. A. Leunissen, M. Jurxzak, M. Benndorf, R. Rooyackers, K. Ronse, S. Decoutere, W. Sansen, and H. E. Maes, "Experimental investigation of the impact of line edge roughness on MOSFET performance and yield," in Proc. ESSDERC, 2003, pp. 227-230.
-
(2003)
Proc. ESSDERC
, pp. 227-230
-
-
Groon, J.A.1
Leunissen, L.H.A.2
Jurxzak, M.3
Benndorf, M.4
Rooyackers, R.5
Ronse, K.6
Decoutere, S.7
Sansen, W.8
Maes, H.E.9
-
13
-
-
0042532317
-
Intrinsic parameter fluctuations in decananometre MOSFETs introduced by gate line edge roughness
-
May
-
A. Asenov, S. Kaya, and A. R. Brown, "Intrinsic parameter fluctuations in decananometre MOSFETs introduced by gate line edge roughness," IEEE Trans. Electron Devices, vol. 50, no. 5, pp. 1254-1260, May 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.5
, pp. 1254-1260
-
-
Asenov, A.1
Kaya, S.2
Brown, A.R.3
-
14
-
-
0036247929
-
Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations
-
Jan
-
A. Asenov, S. Kaya, and J. H. Davies, "Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations," IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 112-119, Jan. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.1
, pp. 112-119
-
-
Asenov, A.1
Kaya, S.2
Davies, J.H.3
-
15
-
-
0346332488
-
Quantum mechanical effects on random oxide thickness and random dopant induced fluctuations in ultrasmall semiconductor devices
-
Dec
-
P. Andrei and I. Mayergoyz, "Quantum mechanical effects on random oxide thickness and random dopant induced fluctuations in ultrasmall semiconductor devices," J. Appl. Phys., vol. 94, no. 11, pp. 7163-7172, Dec. 2003.
-
(2003)
J. Appl. Phys
, vol.94
, Issue.11
, pp. 7163-7172
-
-
Andrei, P.1
Mayergoyz, I.2
-
16
-
-
0842331392
-
Atomistic 3-D process/device simulation considering gate line edge roughness and poly-Si random crystal orientation effects
-
M. Hane, T. Ikezawa, and T. Ezaki, "Atomistic 3-D process/device simulation considering gate line edge roughness and poly-Si random crystal orientation effects," in IEDM Tech. Dig., 2003, pp. 241-244.
-
(2003)
IEDM Tech. Dig
, pp. 241-244
-
-
Hane, M.1
Ikezawa, T.2
Ezaki, T.3
-
17
-
-
0027813761
-
Three-dimensional 'atomistic' simulation of discrete random dopant distribution effects in sub-0.1 mm MOSFETs
-
H.-S. Wong and Y. Taur, "Three-dimensional 'atomistic' simulation of discrete random dopant distribution effects in sub-0.1 mm MOSFETs," in IEDM Tech. Dig., 1993, pp. 705-708.
-
(1993)
IEDM Tech. Dig
, pp. 705-708
-
-
Wong, H.-S.1
Taur, Y.2
-
18
-
-
0026837975
-
Effects of mesoscopic fluctuations in dopant distributions on MOSFET threshold voltage
-
Mar
-
K. Nishiohara, N. Shiguo, and T. Wada, "Effects of mesoscopic fluctuations in dopant distributions on MOSFET threshold voltage," IEEE Trans. Electron Devices, vol. 39, no. 3, pp. 634-639. Mar. 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, Issue.3
, pp. 634-639
-
-
Nishiohara, K.1
Shiguo, N.2
Wada, T.3
-
19
-
-
0032320827
-
Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFETs: A 3-D 'atomistic' simulation study
-
Dec
-
A. Asenov, "Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFETs: A 3-D 'atomistic' simulation study," IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 2505-2513, Dec. 1998.
-
(1998)
IEEE Trans. Electron Devices
, vol.45
, Issue.12
, pp. 2505-2513
-
-
Asenov, A.1
-
20
-
-
0033281305
-
Monte Carlo modeling of threshold variation due to dopant fluctuations
-
D. J. Frank, Y. Taur, M. Ieong, and H.-S. P. Wong, "Monte Carlo modeling of threshold variation due to dopant fluctuations," in VLSI Symp. Tech. Dig., 1999, pp. 169-170.
-
(1999)
VLSI Symp. Tech. Dig
, pp. 169-170
-
-
Frank, D.J.1
Taur, Y.2
Ieong, M.3
Wong, H.-S.P.4
-
21
-
-
0037087352
-
Three-dimensional simulation of ultrasmall metal-oxide-scmiconductor field effect transistors: The role of the discrete impurities on the device terminal characteristics
-
Mar
-
W. J. Goss, D. Vasileska, and D. K. Ferry, "Three-dimensional simulation of ultrasmall metal-oxide-scmiconductor field effect transistors: The role of the discrete impurities on the device terminal characteristics," J. Appl. Phys, vol. 91, no. 6, pp. 3737-3740. Mar. 2002.
-
(2002)
J. Appl. Phys
, vol.91
, Issue.6
, pp. 3737-3740
-
-
Goss, W.J.1
Vasileska, D.2
Ferry, D.K.3
-
22
-
-
33947195764
-
Modelling line edge roughness effects in sub 100 nm gate length devices
-
P. Oldiges, Q. Lin, K. Pertillo, M. Sanchez, M. Ieong, and M. Hargrove, "Modelling line edge roughness effects in sub 100 nm gate length devices," in Proc. SISPAD, 2000, p. 31.
-
(2000)
Proc. SISPAD
, pp. 31
-
-
Oldiges, P.1
Lin, Q.2
Pertillo, K.3
Sanchez, M.4
Ieong, M.5
Hargrove, M.6
-
23
-
-
0036928972
-
Determination of the line edge roughness specification for 34-nm devices
-
T. Linton, M. Chandhok, B. J. Rice, and G. Schrom, "Determination of the line edge roughness specification for 34-nm devices," in IEDM Tech. Dig., 2002, pp. 303-306.
-
(2002)
IEDM Tech. Dig
, pp. 303-306
-
-
Linton, T.1
Chandhok, M.2
Rice, B.J.3
Schrom, G.4
-
24
-
-
0041537563
-
Intrinsic fluctuations in sub 10 nm double-gate MOSFETs introduced by discreteness of charge and matter
-
Dec
-
A. R. Brown, A. Asenov, and J. R. Watling, "Intrinsic fluctuations in sub 10 nm double-gate MOSFETs introduced by discreteness of charge and matter," IEEE Trans. Nanotechnol., vol. 1, no. 4, pp. 195-200, Dec. 2002.
-
(2002)
IEEE Trans. Nanotechnol
, vol.1
, Issue.4
, pp. 195-200
-
-
Brown, A.R.1
Asenov, A.2
Watling, J.R.3
-
25
-
-
24944468332
-
Intrinsic parameter fluctuations in conventional MOSFETs at the scaling limit: A statistical study
-
Oct
-
F. Adamu-Lema, G. Roy, A. R. Brown, A. Asenov, and S. Roy, "Intrinsic parameter fluctuations in conventional MOSFETs at the scaling limit: A statistical study," J. Comput. Electron., vol. 3, no. 3/4, pp. 203-206, Oct. 2004.
-
(2004)
J. Comput. Electron
, vol.3
, Issue.3-4
, pp. 203-206
-
-
Adamu-Lema, F.1
Roy, G.2
Brown, A.R.3
Asenov, A.4
Roy, S.5
-
26
-
-
20344371004
-
Quantum mechanical and transport aspects of resolving discrete charges in nano-CMOS device simulation
-
Munich, Germany
-
A. Asenov, G. Roy, C. Alexander, A. R. Brown, J. R. Watling, and S. Roy, "Quantum mechanical and transport aspects of resolving discrete charges in nano-CMOS device simulation," in Proc. 4th IEEE Conf. Nanotechnol., Munich, Germany, 2004, pp. 334-336.
-
(2004)
Proc. 4th IEEE Conf. Nanotechnol
, pp. 334-336
-
-
Asenov, A.1
Roy, G.2
Alexander, C.3
Brown, A.R.4
Watling, J.R.5
Roy, S.6
-
27
-
-
33751433581
-
Simulation of combined sources of intrinsic parameter fluctuations in a 'Real' 35 nm MOSFET
-
Grenoble, France
-
G. Roy, F. Adamu-Lema, A. R. Brown, S. Roy, and A. Asenov, "Simulation of combined sources of intrinsic parameter fluctuations in a 'Real' 35 nm MOSFET," in Proc. ESSDERC, Grenoble, France, 2005, pp. 337-340.
-
(2005)
Proc. ESSDERC
, pp. 337-340
-
-
Roy, G.1
Adamu-Lema, F.2
Brown, A.R.3
Roy, S.4
Asenov, A.5
-
29
-
-
4544276950
-
A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices
-
N. Yasutake, K. Ohuchi, M. Fujiwara, K. Adachi, A. Hokazono, K. Kojima, N. Aoki, H. Suto, T. Watanabe, T. Morooka, H. Misuno, S. Magoshi, T. Shimizu, S. Mori, H. Oguma, T. Sasaki, M. Ohmura, K. Miyano, H. Yamada, H. Tomita, D. Matsushita, K. Muraoka, S. Inaha, M. Takayanagi, K. Ishimaru, and H. Ishiuchi, "A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices." in VLSI Symp. Tech. Dig., 2004, pp. 84-85.
-
(2004)
VLSI Symp. Tech. Dig
, pp. 84-85
-
-
Yasutake, N.1
Ohuchi, K.2
Fujiwara, M.3
Adachi, K.4
Hokazono, A.5
Kojima, K.6
Aoki, N.7
Suto, H.8
Watanabe, T.9
Morooka, T.10
Misuno, H.11
Magoshi, S.12
Shimizu, T.13
Mori, S.14
Oguma, H.15
Sasaki, T.16
Ohmura, M.17
Miyano, K.18
Yamada, H.19
Tomita, H.20
Matsushita, D.21
Muraoka, K.22
Inaha, S.23
Takayanagi, M.24
Ishimaru, K.25
Ishiuchi, H.26
more..
-
30
-
-
0033312006
-
Hierarchical approach to 'atomistic' 3-D MOSFET simulation
-
Nov
-
A. Asenov, A. R. Brown, J. H. Davies, and S. Saini, "Hierarchical approach to 'atomistic' 3-D MOSFET simulation," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 11, pp. 1558-1565, Nov. 1999.
-
(1999)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst
, vol.18
, Issue.11
, pp. 1558-1565
-
-
Asenov, A.1
Brown, A.R.2
Davies, J.H.3
Saini, S.4
-
31
-
-
0035307248
-
Increase in the random dopant induced threshold fluctuations and lowering in sub 100 nm MOSFETs due to quantum effects: A 3-D density-gradient simulation study
-
Apr
-
A. Asenov, G. Slavcheva, A. R. Brown, J. H. Davies, and S. Saini, "Increase in the random dopant induced threshold fluctuations and lowering in sub 100 nm MOSFETs due to quantum effects: A 3-D density-gradient simulation study," IEEE Trans. Electron Devices, vol. 48, no. 4, pp. 722-729, Apr. 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, Issue.4
, pp. 722-729
-
-
Asenov, A.1
Slavcheva, G.2
Brown, A.R.3
Davies, J.H.4
Saini, S.5
-
32
-
-
0037004304
-
High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide
-
Dec
-
S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. linuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, "High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide," IEEE Trans. Electron Devices, vol. 49. no. 12, pp. 2263-2270. Dec. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.12
, pp. 2263-2270
-
-
Inaba, S.1
Okano, K.2
Matsuda, S.3
Fujiwara, M.4
Hokazono, A.5
Adachi, K.6
Ohuchi, K.7
Suto, H.8
Fukui, H.9
Shimizu, T.10
Mori, S.11
Oguma, H.12
Murakoshi, A.13
Itani, T.14
linuma, T.15
Kudo, T.16
Shibata, H.17
Taniguchi, S.18
Takayanagi, M.19
Azuma, A.20
Oyamatsu, H.21
Suguro, K.22
Katsumata, Y.23
Toyoshima, Y.24
Ishiuchi, H.25
more..
-
33
-
-
0036473348
-
On discrete random dopant modelling in drift-diffusion simulations: Physical meaning of 'atomistic' dopants
-
Feb
-
N. Sano, K. Matsuzawa, M. Mukai, and N. Nakayama, "On discrete random dopant modelling in drift-diffusion simulations: Physical meaning of 'atomistic' dopants," Microelectron. Reliab., vol. 42, no. 2, pp. 189-199, Feb. 2002.
-
(2002)
Microelectron. Reliab
, vol.42
, Issue.2
, pp. 189-199
-
-
Sano, N.1
Matsuzawa, K.2
Mukai, M.3
Nakayama, N.4
-
34
-
-
3142706175
-
The use of quantum potentials for confinement and tunnelling in semiconductor devices
-
Dec
-
A. Asenov, J. R. Watling, A. R. Brown, and D. K. Ferry, "The use of quantum potentials for confinement and tunnelling in semiconductor devices," J. Comput. Electron., vol. 1, no. 4, pp. 503-513, Dec. 2002.
-
(2002)
J. Comput. Electron
, vol.1
, Issue.4
, pp. 503-513
-
-
Asenov, A.1
Watling, J.R.2
Brown, A.R.3
Ferry, D.K.4
-
35
-
-
84948782220
-
Integrated atomistic process and device simulation of decananometre MOSFETs
-
IEEE cat. 02TH8621
-
A. Asenov, M. Jaraiz, S. Roy, G. Roy, F. Adamu-Lema, A. R. Brown, V. Moroz, and R. Gafiteanu,' "Integrated atomistic process and device simulation of decananometre MOSFETs," in Proc. SISPAD, 2002, pp. 87-90. IEEE cat. 02TH8621.
-
(2002)
Proc. SISPAD
, pp. 87-90
-
-
Asenov, A.1
Jaraiz, M.2
Roy, S.3
Roy, G.4
Adamu-Lema, F.5
Brown, A.R.6
Moroz, V.7
Gafiteanu, R.8
-
36
-
-
3242675991
-
Bipolar quantum corrections in resolving individual dopants in 'atomistic' device simulations
-
Sep./Dec
-
G. Roy, A. R. Brown, A. Asenov, and S. Roy, "Bipolar quantum corrections in resolving individual dopants in 'atomistic' device simulations," Superlattices Microstruct., vol. 34, no. 3-6, pp. 327-334, Sep./Dec. 2004.
-
(2004)
Superlattices Microstruct
, vol.34
, Issue.3-6
, pp. 327-334
-
-
Roy, G.1
Brown, A.R.2
Asenov, A.3
Roy, S.4
-
38
-
-
0033169519
-
Suppression of random dopant induced threshold voltage fluctuations in sub-0.1 μm MOSFETs with epitaxial and delta doped channels
-
Aug
-
A. Asenov and S. Saini, "Suppression of random dopant induced threshold voltage fluctuations in sub-0.1 μm MOSFETs with epitaxial and delta doped channels," IEEE Trans. Electron Devices, vol. 46, no. 8, pp. 1718-1724, Aug. 1999.
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, Issue.8
, pp. 1718-1724
-
-
Asenov, A.1
Saini, S.2
-
39
-
-
33745131794
-
Direct measurement of effects of shallowtrench isolation on carrier profiles in sub-50 nm n-MOSFETs
-
H. Fukutome, Y. Momiyama, Y. Tagawa, T. Kubo, T. Aoyama, H. Arimoto, and Y. Nara, "Direct measurement of effects of shallowtrench isolation on carrier profiles in sub-50 nm n-MOSFETs," in VLSI Symp. Tech. Dig., 2005, pp. 140-141.
-
(2005)
VLSI Symp. Tech. Dig
, pp. 140-141
-
-
Fukutome, H.1
Momiyama, Y.2
Tagawa, Y.3
Kubo, T.4
Aoyama, T.5
Arimoto, H.6
Nara, Y.7
-
40
-
-
4544387565
-
-
F. Arnaud, B. Duriez, B. Tavel, L. Pain, J. Todeschini, M. Jurdit, Y. Laplanche, F. Boeuf, F. Salvetti, D. Lenoble, J. P. Reynard, F. Wacquant, P. Morin, N. Emonet, D. Barge, M. Bidaud, D. Ceccarelli, P. Vannier, Y. Loquet, H. Leninger, F. Judong, C. Perrot, I. Guilmeau, R. Palla, A. Beverina, V. DeJonghe, M. Brockaart, V. Vachellerie, R. A. Blanchi, B. Borot, T. Devoivre, N. Bicaïs, D. Roy, M. Denais, K. Rochereau, R. Difrenza, N. Planes, H. Brut, L. Vishnobulta, D. Reber, P. Stolk, and M. Woo, Low cost 65 nm CMOS platform for low power and general purposes applications, in VLSI Symp. Tech. Dig., 2004, pp. 10-11.
-
F. Arnaud, B. Duriez, B. Tavel, L. Pain, J. Todeschini, M. Jurdit, Y. Laplanche, F. Boeuf, F. Salvetti, D. Lenoble, J. P. Reynard, F. Wacquant, P. Morin, N. Emonet, D. Barge, M. Bidaud, D. Ceccarelli, P. Vannier, Y. Loquet, H. Leninger, F. Judong, C. Perrot, I. Guilmeau, R. Palla, A. Beverina, V. DeJonghe, M. Brockaart, V. Vachellerie, R. A. Blanchi, B. Borot, T. Devoivre, N. Bicaïs, D. Roy, M. Denais, K. Rochereau, R. Difrenza, N. Planes, H. Brut, L. Vishnobulta, D. Reber, P. Stolk, and M. Woo, "Low cost 65 nm CMOS platform for low power and general purposes applications," in VLSI Symp. Tech. Dig., 2004, pp. 10-11.
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