FinFET SRAM: Optimizing silicon fin thickness and fin ratio to improve stability at iso area

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2007, Pages 623-626

  Lekshmanan, Dheepa ^a   Bansal, Aditya ^a   Roy, Kaushik ^a  

^a Purdue University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONSTRAINT THEORY; INTEGRATED CIRCUITS; SILICON; TRANSISTORS;

FINFETS; SILICON FIN THICKNESS;

STATIC RANDOM ACCESS STORAGE;

EID: 39549119842     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405809     Document Type: Conference Paper

References (17)

1. D. Hisamoto et. al., IEEE TED, Dec 2000, pp. 2320-2325.
2. B.Yu et. al., IEDM, 2002, pp. 251-254
3. H. Ananthan et. al. ISQED, 2004, pp. 511-516.
4. A. Bansal et. al. IEEE CICC, 2005, pp. 835-838.
5. S. Gangwal et. al., IEEE CICC, 2006, pp. 433-436.
6. S. Xiong et. al. IEEE TED, Nov. 2003, pp. 2255-2261.
7. D. Esseni et. al., IEEE TED, 2003, pp. 2445-2455.
8. Taurus Device Simulator, Synopsys Inc., v W-2004.09.
9. P. Ranade, et. al., IEDM, 2002, pp. 363-366.
10. H. Kawasaki et. al. VLSI Tech Sym , Jun.2006, pp.70-71.
11. Yang-Kyu Choi et. al., IEEE EDL, Jan 2002, pp25-27.
12. E. Seevinck et. al., JSSC Oct 1987, pp. 748-754.
13. K. Takeda et. al., ISSCC, Feb 2005, pp. 2602-2611.
14. S. Mukhopadhyay et. al. IEEE TCAD, 2005, pp. 1859-1880.
15. D.J.Frank et. al., VLSI Tech Sym., 1999, pp. 169-170.
16. A. Bhavnagarwala et. al., IEEE JSSC, April 2001, pp. 658-665.
17. D. Lekshmanan et. al., DRC, 2007.