Impact of line-edge roughness on FinFET matching performance

IEEE Transactions on Electron Devices

Volumn 54, Issue 9, 2007, Pages 2466-2474

  Baravelli, Emanuele ^a,b   Dixit, Abhisek ^a,c   Rooyackers, Rita ^a   Jurczak, Malgorzata ^a   Speciale, Nicolò ^b   De Meyer, Kristin ^a,c  

^a IMEC   (Belgium)

^b UNIVERSITY OF BOLOGNA   (Italy)

^c UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

CMOS technology; FinFET; Fully depleted silicon on insulator (FDSOI); Line edge roughness (LER); Spacerdefined patterning; Transistor matching

Indexed keywords

CMOS INTEGRATED CIRCUITS; SILICON ON INSULATOR TECHNOLOGY; SPECIFICATIONS; STATIC RANDOM ACCESS STORAGE;

FULLY DEPLETED SILICON-ON INSULATOR; LINE-EDGE ROUGHNESS; RESIST-DEFINED FIN PATTERNING; SPACER-DEFINED FIN PATTERNING; TRANSISTOR MATCHING;

FIELD EFFECT TRANSISTORS;

EID: 41749084658     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.902166     Document Type: Article

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