메뉴 건너뛰기




Volumn , Issue , 2006, Pages 258-261

Impact of random dopant fluctuation on bulk CMOS 6-T SRAM scaling

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; MOSFET DEVICES; SCALABILITY;

EID: 84943197898     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2006.307687     Document Type: Conference Paper
Times cited : (40)

References (15)
  • 1
    • 84943203780 scopus 로고    scopus 로고
    • A. Asenov, 3D statistical simulation of intrinsic fluctuations in decanano MOSFETs induced by discrete dopants, oxide thickness fluctuations and LER, Proc. SISPAD2001, pp. 162-169, 2001.
    • A. Asenov, "3D statistical simulation of intrinsic fluctuations in decanano MOSFETs induced by discrete dopants, oxide thickness fluctuations and LER," Proc. SISPAD2001, pp. 162-169, 2001.
  • 2
    • 21644432592 scopus 로고    scopus 로고
    • A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57μm2 SRAM Cell
    • P. Bai, C.Auth, S.Balakrisnnan, M.Bost, R. Brain, V. Chikarmane, et al, "A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57μm2 SRAM Cell," Tech. Digest of IEDM, pp. 657-660, 2004.
    • (2004) Tech. Digest of IEDM , pp. 657-660
    • Bai, P.1    Auth, C.2    Balakrisnnan, S.3    Bost, M.4    Brain, R.5    Chikarmane, V.6
  • 3
    • 21644472774 scopus 로고    scopus 로고
    • A 0.314/spl mu/m/sup 2/6T-SRAM cell build with tall tripe-gate devices for 45nm applications using 0.75NA 193nm lithography
    • A. Nackaerts, M. Ercken, S. Demuynck, A. Lauwers, C. Baerts, H. Bender, et al, "A 0.314/spl mu/m/sup 2/6T-SRAM cell build with tall tripe-gate devices for 45nm applications using 0.75NA 193nm lithography," Tech. Digest of IEDM, pp. 269-272, 2004.
    • (2004) Tech. Digest of IEDM , pp. 269-272
    • Nackaerts, A.1    Ercken, M.2    Demuynck, S.3    Lauwers, A.4    Baerts, C.5    Bender, H.6
  • 5
    • 0035445204 scopus 로고    scopus 로고
    • A study of the threshold voltage variation for ultra-small bulk and SOI CMOS
    • K. Takeuchi, R. Koh, T. Mogami, "A study of the threshold voltage variation for ultra-small bulk and SOI CMOS," IEEE Trans on Elec. Dev., vol.48, pp.1995-2001, 2001.
    • (2001) IEEE Trans on Elec. Dev , vol.48 , pp. 1995-2001
    • Takeuchi, K.1    Koh, R.2    Mogami, T.3
  • 6
    • 0035308547 scopus 로고    scopus 로고
    • The impact of intrinsic device fluctuations on CMOS SRAM cell stability
    • A. Bhavnagarwala, X. Tang, J. D. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE J. Solid-State Circuits, vol. 36, pp.658-665, 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , pp. 658-665
    • Bhavnagarwala, A.1    Tang, X.2    Meindl, J.D.3
  • 7
    • 14844337078 scopus 로고    scopus 로고
    • Impact of intrinsic parameter fluctuations in decanano MOSFETs on yield and functionality of SRAM cells
    • B. Cheng, S. Roy, G. Roy, F. Adamu-Lema, A. Asenov, "Impact of intrinsic parameter fluctuations in decanano MOSFETs on yield and functionality of SRAM cells," Solid-State Electronics, vol. 49, pp. 740-746, 2005.
    • (2005) Solid-State Electronics , vol.49 , pp. 740-746
    • Cheng, B.1    Roy, S.2    Roy, G.3    Adamu-Lema, F.4    Asenov, A.5
  • 8
    • 33751393874 scopus 로고    scopus 로고
    • UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation
    • K. Samsudin, B. Cheng, A. R. Brown, S. Roy, A. Asenov, "UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation," Proc. ESSDERC 2005, pp. 553-556, 2005 .
    • (2005) Proc. ESSDERC 2005 , pp. 553-556
    • Samsudin, K.1    Cheng, B.2    Brown, A.R.3    Roy, S.4    Asenov, A.5
  • 11
    • 84943203781 scopus 로고    scopus 로고
    • http://www.itrs.net/Common/2003ITRS/Home2003.htm
  • 12
    • 33751433581 scopus 로고    scopus 로고
    • Simulation of Combined Sources of Intrinsic Parameter Fluctuations in a 'Real' 35 nm MOSFET
    • G. Roy, F. Adamu-Lema, A. R. Brown, S. Roy and A. Asenov, "Simulation of Combined Sources of Intrinsic Parameter Fluctuations in a 'Real' 35 nm MOSFET," Proc. ESSDERC, pp.337-340, 2005
    • (2005) Proc. ESSDERC , pp. 337-340
    • Roy, G.1    Adamu-Lema, F.2    Brown, A.R.3    Roy, S.4    Asenov, A.5
  • 13
    • 0037004304 scopus 로고    scopus 로고
    • High performance 35nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide
    • S. Inaba, K. Okano, S. Matsuda, et al., "High performance 35nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide," IEEE Trans on Elec. Dev. Vol. 49, pp.2263-2270, 2002
    • (2002) IEEE Trans on Elec. Dev , vol.49 , pp. 2263-2270
    • Inaba, S.1    Okano, K.2    Matsuda, S.3
  • 14
    • 84943203782 scopus 로고    scopus 로고
    • C. Alexander, A. R. Brown, J. R. Watling, and A. Asenov, Impact of Scattering on Random Dopant Induced Current Fluctuations in Decanano MOSFETs, Proc. SISPAD2004, pp.223-226, 2004.
    • C. Alexander, A. R. Brown, J. R. Watling, and A. Asenov, "Impact of Scattering on Random Dopant Induced Current Fluctuations in Decanano MOSFETs," Proc. SISPAD2004, pp.223-226, 2004.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.