-
1
-
-
0000610932
-
Passive interconnect reduction algorithm for distributed/measured networks
-
April
-
R. Achar, P. K. Gunupudi, M. Nakhla, and E. Chiprout, –Passive interconnect reduction algorithm for distributed/measured networks, — IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, 47, (4), 287-301, April 2000.
-
(2000)
IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing
, vol.47
, Issue.4
, pp. 287-301
-
-
Achar, R.1
Gunupudi, P.K.2
Nakhla, M.3
Chiprout, E.4
-
3
-
-
0043136760
-
Realizable rlck circuit crunching
-
C. S. Amin, M. H. Chowdhury, and Y. I. Ismail, –Realizable RLCK circuit crunching, — in Proc. Design Automation Conf. (DAC), 2003, 226-231.
-
(2003)
Proc. Design Automation Conf. (DAC)
, pp. 226-231
-
-
Amin, C.S.1
Chowdhury, M.H.2
Ismail, Y.I.3
-
4
-
-
0001076547
-
A system theory criterion for positive real matrices
-
B. D. O. Anderson, –A system theory criterion for positive real matrices, — SIAM J. Contr., 5, 171-182, 1967.
-
(1967)
SIAM J. Contr
, vol.5
, pp. 171-182
-
-
Anderson, B.1
-
6
-
-
4544371785
-
Approximation of large-scale dynamical system: An overview
-
A. Antoulas and D. C. Sorensen, –Approximation of large-scale dynamical system: An overview, — Int. J. Appl. Math. Comput. Sci., 11, (5), 1093-1121, 2001.
-
(2001)
Int. J. Appl. Math. Comput. Sci
, vol.11
, Issue.5
, pp. 1093-1121
-
-
Antoulas, A.1
Sorensen, D.C.2
-
7
-
-
0021618667
-
Generalized eigenproblem algorithms and software for algebraic riccati equation
-
W. F. Arnold and A. J. Laub, –Generalized eigenproblem algorithms and software for algebraic Riccati equation, — Proc. IEEE, 72, 1764-1754, 1984.
-
(1984)
Proc. IEEE
, vol.72
, pp. 1754-1764
-
-
Arnold, W.F.1
Laub, A.J.2
-
8
-
-
0002807741
-
The principle of minimized iteration in the solution of the matrix eigenvalue problem
-
W. E. Arnoldi, –The principle of minimized iteration in the solution of the matrix eigenvalue problem, — Quat. Appl. Math., 9, 17-29, 1951.
-
(1951)
Quat. Appl. Math
, vol.9
, pp. 17-29
-
-
Arnoldi, W.E.1
-
10
-
-
0242406989
-
State-space truncation methods for parallel model reduction of large-scale systems
-
P. Benner, E. S. Quintana-Orti, and G. Quintana-Orti, –State-space truncation methods for parallel model reduction of large-scale systems, — Parallel Comput., 29, (11-12), 1701-1722, 2003.
-
(2003)
Parallel Comput
, vol.29
, Issue.11-12
, pp. 1701-1722
-
-
Benner, P.1
Quintana-Orti, E.S.2
Quintana-Orti, G.3
-
11
-
-
0034825980
-
Design of robust global power and ground networks
-
S. Boyd, L. Vandenberghe, A. E. Gamal, and S. Yun, –Design of robust global power and ground networks, — in Proc. ACM Int. Symp. on Physical Design (ISPD), 2001.
-
(2001)
Proc. ACM Int. Symp. on Physical Design (ISPD)
-
-
Boyd, S.1
Vandenberghe, L.2
Gamal, A.E.3
Yun, S.4
-
12
-
-
85162672236
-
Synthesis of a finite two-terminal network whose driving point impedance is a prescribed function of frequency
-
O. Brune, –Synthesis of a finite two-terminal network whose driving point impedance is a prescribed function of frequency, — Journal of Math. and Phys., 10, 191-236, 1931.
-
(1931)
Journal of Math. and Phys
, vol.10
, pp. 191-236
-
-
Brune, O.1
-
13
-
-
85025638815
-
Impedance synthesis without transformers
-
R. Brune and R. Duffin, –Impedance synthesis without transformers, — J. of Appl. Phys., 20, 816, 1949.
-
(1949)
J. of Appl. Phys
, vol.20
-
-
Brune, R.1
Duffin, R.2
-
16
-
-
0038444634
-
Inductwise: Inductance-wise interconnect simulator and extractor
-
T. Chen, C. Luk, and C. Chen, –Inductwise: Inductance-wise interconnect simulator and extractor, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 22, (7), 884-894, 2003.
-
(2003)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.22
, Issue.7
, pp. 884-894
-
-
Chen, T.1
Luk, C.2
Chen, C.3
-
17
-
-
0036911569
-
Inductwise: Inductance-wise interconnect simulator and extractor
-
T. Chen, C. Luk, H. Kim, and C. Chen, –INDUCTWISE: Inductance-wise interconnect simulator and extractor, — in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2002.
-
(2002)
Proc. Int. Conf. on Computer Aided Design (ICCAD)
-
-
Chen, T.1
Luk, C.2
Kim, H.3
Chen, C.4
-
18
-
-
16244415873
-
Fast ip-chip power grid analysis via locality and grid shells
-
Nov
-
E. Chiprout, –Fast ip-chip power grid analysis via locality and grid shells, — in Proc. Int. Conf. on Computer Aided Design (ICCAD), Nov. 2004, 485-488.
-
(2004)
Proc. Int. Conf. on Computer Aided Design (ICCAD)
, pp. 485-488
-
-
Chiprout, E.1
-
19
-
-
0029250497
-
Analysis of interconnect networks using complex frequency hopping
-
Feb
-
E. Chiprout and M. S. Nakhla, –Analysis of interconnect networks using complex frequency hopping, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 14, (2), 186-200, Feb. 1995.
-
(1995)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.14
, Issue.2
, pp. 186-200
-
-
Chiprout, E.1
Nakhla, M.S.2
-
21
-
-
1242308409
-
A convex programming approach for generating guaranteed passive approximations to tabulated frequency-data
-
Feb
-
C. P. Coelho, J. Phillips, and L. M. Silveira, –A convex programming approach for generating guaranteed passive approximations to tabulated frequency-data, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 23, (2), 293-301, Feb. 2004.
-
(2004)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.23
, Issue.2
, pp. 293-301
-
-
Coelho, C.P.1
Phillips, J.2
Silveira, L.M.3
-
22
-
-
0035215676
-
A convex programming approach to positive real rational approximation
-
Nov
-
C. P. Coelho, J. R. Phillips, and L. M. Silveira, –A convex programming approach to positive real rational approximation, — in Proc. Int. Conf. on Computer Aided Design (ICCAD), Nov. 2001, 245-251.
-
(2001)
Proc. Int. Conf. on Computer Aided Design (ICCAD)
, pp. 245-251
-
-
Coelho, C.P.1
Phillips, J.R.2
Silveira, L.M.3
-
23
-
-
0030291640
-
Performance optimization of vlsi interconnect layout
-
Nov
-
J. Cong, L. He, C.-K. Koh, and P. Padden, –Performance optimization of VLSI interconnect layout, — Integration, the VLSI Journal, 21, (1-2), 1-94, Nov 1996.
-
(1996)
Integration, the VLSI Journal
, vol.21
, Issue.1-2
, pp. 1-94
-
-
Cong, J.1
He, L.2
Koh, C.-K.3
Padden, P.4
-
25
-
-
0034474751
-
How to efficiently capture on-chip inductance effects: Introducing a new circuit element k
-
A. Devgan, H. Ji, and W. Dai, –How to efficiently capture on-chip inductance effects: introducing a new circuit element K, — in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2000, 150-155.
-
(2000)
Proc. Int. Conf. on Computer Aided Design (ICCAD)
, pp. 150-155
-
-
Devgan, A.1
Ji, H.2
Dai, W.3
-
27
-
-
0029735239
-
Including higher-order moments of rc interconnections in layout-to-circuit extraction
-
P. Elias and N. van der Meijs, –Including higher-order moments of RC interconnections in layout-to-circuit extraction, — in Proc. European Design and Test Conf. (DATE), 1996, 362-366.
-
(1996)
Proc. European Design and Test Conf. (DATE)
, pp. 362-366
-
-
Elias, P.1
Van Der Meijs, N.2
-
28
-
-
34748823693
-
The transient analysis of damped linear networks with particular regard to wideband amplifiers
-
W. C. Elmore, –The transient analysis of damped linear networks with particular regard to wideband amplifiers, — J. Appl. Phys., 1948.
-
(1948)
J. Appl. Phys
-
-
Elmore, W.C.1
-
29
-
-
0021641650
-
Model reduction with balanced realizations: An error bound and frequency weighted generalization
-
D. F. Enns, –Model reduction with balanced realizations: an error bound and frequency weighted generalization, — in Proc. 23th IEEE Conf. Decision and Control, 1984, 127-132.
-
(1984)
Proc. 23Th IEEE Conf. Decision and Control
, pp. 127-132
-
-
Enns, D.F.1
-
31
-
-
3042515430
-
Model order reduction techniques for linear systems with large numbers of terminals
-
P. Feldmann, –Model order reduction techniques for linear systems with large numbers of terminals, — in Proc. European Design and Test Conf. (DATE), 2004, 944-947.
-
(2004)
Proc. European Design and Test Conf. (DATE)
, pp. 944-947
-
-
Feldmann, P.1
-
32
-
-
0029308198
-
Efficient linear circuit analysis by pade approximation via the lanczos process
-
May
-
P. Feldmann and R. W. Freund, –Efficient linear circuit analysis by Pade approximation via the Lanczos process, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 14, (5), 639-649, May 1995.
-
(1995)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.14
, Issue.5
, pp. 639-649
-
-
Feldmann, P.1
Freund, R.W.2
-
33
-
-
0141849837
-
Reduced-order modeling of large linear subcircuits via block lanczos algorithm
-
P. Feldmann and R. W. Freund, –Reduced-order modeling of large linear subcircuits via block lanczos algorithm, — in Proc. Design Automation Conf. (DAC), 1995, 376-380.
-
(1995)
Proc. Design Automation Conf. (DAC)
, pp. 376-380
-
-
Feldmann, P.1
Freund, R.W.2
-
34
-
-
16244418081
-
Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals
-
P. Feldmann and F. Liu, –Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals, — in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2004, 88-92.
-
(2004)
Proc. Int. Conf. on Computer Aided Design (ICCAD)
, pp. 88-92
-
-
Feldmann, P.1
Liu, F.2
-
35
-
-
0002917491
-
Reduced-order modeling of large linear passive multiterminal circuits using matrix-pade approximation
-
R. Freund and P. Feldmann, –Reduced-order modeling of large linear passive multiterminal circuits using matrix-Pade approximation, — in Proc. European Design and Test Conf. (DATE), 1998, 530-537.
-
(1998)
Proc. European Design and Test Conf. (DATE)
, pp. 530-537
-
-
Freund, R.1
Feldmann, P.2
-
36
-
-
0032638526
-
Passive reduced-order modeling of interconnects simulation and their computation by krylov-subspace algorithm
-
R. W. Freund, –Passive reduced-order modeling of interconnects simulation and their computation by Krylov-subspace algorithm, — in Proc. Design Automation Conf. (DAC), 1999, 195-200.
-
(1999)
Proc. Design Automation Conf. (DAC)
, pp. 195-200
-
-
Freund, R.W.1
-
37
-
-
16244364781
-
Sprim: Structure-preserving reduced-order interconnect macromodeling
-
R. W. Freund, –SPRIM: structure-preserving reduced-order interconnect macromodeling, — in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2004, 80-87.
-
(2004)
Proc. Int. Conf. on Computer Aided Design (ICCAD)
, pp. 80-87
-
-
Freund, R.W.1
-
38
-
-
0030397409
-
Reduced-order modeling of large linear subcircuits by means of the sypvl algorithm
-
R. W. Freund and P. Feldmann, –Reduced-order modeling of large linear subcircuits by means of the SyPVL algorithm, — in Proc. Int. Conf. on Computer Aided Design (ICCAD), 1996, 280-287.
-
(1996)
Proc. Int. Conf. on Computer Aided Design (ICCAD)
, pp. 280-287
-
-
Freund, R.W.1
Feldmann, P.2
-
39
-
-
0030397409
-
Reduced-order modeling of large linear subcircuits by means of the sypvl algorithm
-
R. W. Freund and P. Feldmann, –Reduced-order modeling of large linear subcircuits by means of the sypvl algorithm, — in Proc. Int. Conf. on Computer Aided Design (ICCAD), 1996, 280-287.
-
(1996)
Proc. Int. Conf. on Computer Aided Design (ICCAD)
, pp. 280-287
-
-
Freund, R.W.1
Feldmann, P.2
-
41
-
-
0000195442
-
Computer-aided design of analog and mixed-signal integrated circuits
-
Dec
-
G. Gielen and R. Rutenbar, –Computer-aided design of analog and mixed-signal integrated circuits, — Proc. of IEEE, 88, (12), 703-717, Dec. 2000.
-
(2000)
Proc. of IEEE
, vol.88
, Issue.12
, pp. 703-717
-
-
Gielen, G.1
Rutenbar, R.2
-
43
-
-
0021441691
-
All optimal hankel-norm approximations of linear multivariable systems and their l1-error bounds
-
K. Glover, –All optimal Hankel-norm approximations of linear multivariable systems and their l1-error bounds, — Int. J. Contr., 39, 1115-1193, 1984.
-
(1984)
Int. J. Contr
, vol.39
, pp. 1115-1193
-
-
Glover, K.1
-
46
-
-
0035701572
-
Recent advances in reduced-order modeling of complex interconnects
-
Oct
-
S. Grivet-Talocia, I. A. Maio, and F. Canavero, –Recent advances in reduced-order modeling of complex interconnects, — in Proc. Dig. Electrical Performance Electronic Packaging, Oct. 2001, 243-246, vol. 10.
-
(2001)
Proc. Dig. Electrical Performance Electronic Packaging
, vol.10
, pp. 243-246
-
-
Grivet-Talocia, S.1
Maio, I.A.2
Canavero, F.3
-
48
-
-
0030672184
-
The elmore delay as a bound for rc trees with generalized input signals
-
Jan
-
R. Gupta, B. Tutuianu, and L. Pileggi, –The Elmore delay as a bound for RC trees with generalized input signals, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, (1), 95-104, Jan. 1997.
-
(1997)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, Issue.1
, pp. 95-104
-
-
Gupta, R.1
Tutuianu, B.2
Pileggi, L.3
-
49
-
-
0032666467
-
Rational approximation of frequency domain responses by vector fitting
-
March
-
B. Gustavsen and A. Semlyen, –Rational approximation of frequency domain responses by vector fitting, — IEEE Trans. on Power Delivery, 14, (3), 1052-1061, March 1999.
-
(1999)
IEEE Trans. on Power Delivery
, vol.14
, Issue.3
, pp. 1052-1061
-
-
Gustavsen, B.1
Semlyen, A.2
-
50
-
-
0035248249
-
Enforcing passivity for admittance matrices approximated by rational functions
-
Feb
-
B. Gustavsen and A. Semlyen, –Enforcing passivity for admittance matrices approximated by rational functions, — IEEE Trans. on Power Systems, 16, (1), 97-104, Feb. 2001.
-
(2001)
IEEE Trans. on Power Systems
, vol.16
, Issue.1
, pp. 97-104
-
-
Gustavsen, B.1
Semlyen, A.2
-
51
-
-
0029288199
-
A hierarchical network approach to symbolic analysis of large scale networks
-
April
-
M. M. Hassoun and P. M. Lin, –A hierarchical network approach to symbolic analysis of large scale networks, — IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, 42, (4), 201-211, April 1995.
-
(1995)
IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications
, vol.42
, Issue.4
, pp. 201-211
-
-
Hassoun, M.M.1
Lin, P.M.2
-
52
-
-
0030645057
-
Spie: Sparse partial inductance extraction
-
Z. He, M. Celik, and L. Pillegi, –SPIE: Sparse partial inductance extraction, — in Proc. Design Automation Conf. (DAC), 1997, 137-140.
-
(1997)
Proc. Design Automation Conf. (DAC)
, pp. 137-140
-
-
He, Z.1
Celik, M.2
Pillegi, L.3
-
54
-
-
0036911854
-
Efficient model order reduction via multi-node moment matching
-
Nov
-
Y. Ismail, –Efficient model order reduction via multi-node moment matching, — in Proc. Int. Conf. on Computer Aided Design (ICCAD), Nov. 2002, 767-774.
-
(2002)
Proc. Int. Conf. on Computer Aided Design (ICCAD)
, pp. 767-774
-
-
Ismail, Y.1
-
56
-
-
0036474096
-
Dtt: Direct truncation of the transfer function-an alternative to moment matching for tree structured interconnect
-
Feb
-
Y. Ismail and E. G. Friedman, –DTT: direct truncation of the transfer function-an alternative to moment matching for tree structured interconnect, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 21, (2), 131-144, Feb. 2003.
-
(2003)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.21
, Issue.2
, pp. 131-144
-
-
Ismail, Y.1
Friedman, E.G.2
-
58
-
-
84949799397
-
Ksim: A stable and efficient rkc simulator for capturing on-chip inductance effect
-
H. Ji, A. Devgan, and W. Dai, –Ksim: A stable and efficient RKC simulator for capturing on-chip inductance effect, — in Proc. Asia South Pacific Design Automation Conf. (ASPDAC), 2001, 379-384.
-
(2001)
Proc. Asia South Pacific Design Automation Conf. (ASPDAC)
, pp. 379-384
-
-
Ji, H.1
Devgan, A.2
Dai, W.3
-
59
-
-
0028498583
-
Fasthenry: A multipole-accelerated 3d inductance extraction program
-
Sept
-
M. Kamon, M. Tsuk, and J. White, –FastHenry: a multipole-accelerated 3D inductance extraction program, — IEEE Trans. on Microwave Theory and Techniques, 1750-1758, Sept. 1994.
-
(1994)
IEEE Trans. on Microwave Theory and Techniques
, pp. 1750-1758
-
-
Kamon, M.1
Tsuk, M.2
White, J.3
-
60
-
-
0007870783
-
Generating nearly optimally compact models from krylov-subspace based reduced-order models
-
M. Kamon, F. Wang, and J. White, –Generating nearly optimally compact models from Krylov-subspace based reduced-order models, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 47, (4), 239-248, 2000.
-
(2000)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.47
, Issue.4
, pp. 239-248
-
-
Kamon, M.1
Wang, F.2
White, J.3
-
62
-
-
0033725695
-
A realizable driving point model for on-chip interconnect with inductance
-
C. Kashyap and B. Krauter, –A realizable driving point model for on-chip interconnect with inductance, — in Proc. Design Automation Conf. (DAC), 2000.
-
(2000)
Proc. Design Automation Conf. (DAC)
-
-
Kashyap, C.1
Krauter, B.2
-
63
-
-
0031176801
-
Stable and efficient reduction of large, multiport rc network by pole analysis via congruence transformations
-
July
-
K. J. Kerns and A. T. Yang, –Stable and efficient reduction of large, multiport RC network by pole analysis via congruence transformations, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 16, (7), 734-744, July 1998.
-
(1998)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.16
, Issue.7
, pp. 734-744
-
-
Kerns, K.J.1
Yang, A.T.2
-
66
-
-
84932605547
-
A formal top-down design process for mixed-signal circuits
-
R. J. van de Plassche, J. Huigsing, and W. Sansen, Eds. Kluwer Academic Publishers
-
K. S. Kundert, –A formal top-down design process for mixed-signal circuits, — in Analog Circuit Design, R. J. van de Plassche, J. Huigsing, and W. Sansen, Eds. Kluwer Academic Publishers, 2000.
-
(2000)
Analog Circuit Design
-
-
Kundert, K.S.1
-
67
-
-
0000094594
-
An iteration method for the solution of the eigenvalue problem of linear differential and integral operators
-
C. Lanczos, –An iteration method for the solution of the eigenvalue problem of linear differential and integral operators, — J. Res. Bur. Standards, 45, 255-282, 1950.
-
(1950)
J. Res. Bur. Standards
, vol.45
, pp. 255-282
-
-
Lanczos, C.1
-
68
-
-
0023288081
-
Computation of system balancing transformations and other applications of simultaneous diagonalization algorithms
-
A. J. Laub, M. T. Heath, C. C. Paige, and R. C. Ward, –Computation of system balancing transformations and other applications of simultaneous diagonalization algorithms, — IEEE Trans. Automat. Contr., 32, 115-122, 1987.
-
(1987)
IEEE Trans. Automat. Contr
, vol.32
, pp. 115-122
-
-
Laub, A.J.1
Heath, M.T.2
Paige, C.C.3
Ward, R.C.4
-
69
-
-
7444226472
-
Properties of the singular value decomposition for efficient data clustering
-
Nov
-
S. Lee and M. H. Hayes, –Properties of the singular value decomposition for efficient data clustering, — IEEE Signal Process Letters, 11, (11), 862-866, Nov. 2004.
-
(2004)
IEEE Signal Process Letters
, vol.11
, Issue.11
, pp. 862-866
-
-
Lee, S.1
Hayes, M.H.2
-
71
-
-
20444438679
-
Hiprime: Hierarchical and passivity preserved interconnect macromodeling engine for rlkc power delivery
-
Y. Lee, Y. Cao, T. Chen, J. Wang, and C. Chen, –HiPRIME: Hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 26, (6), 797-806, 2005.
-
(2005)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.26
, Issue.6
, pp. 797-806
-
-
Lee, Y.1
Cao, Y.2
Chen, T.3
Wang, J.4
Chen, C.5
-
73
-
-
33746802399
-
A general method for multi-port active network reduction and realization
-
P. Liu, Z. Qi, A. Aviles, and S. X.-D. Tan, –A general method for multi-port active network reduction and realization, — in Proc. IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), 2005, 7-12.
-
(2005)
Proc. IEEE International Workshop on Behavioral Modeling and Simulation (BMAS)
, pp. 7-12
-
-
Liu, P.1
Qi, Z.2
Aviles, A.3
Tan, S.X.4
-
74
-
-
33751396905
-
Fast thermal simulation for architecture level dynamic thermal management
-
Nov
-
P. Liu, Z. Qi, H. Li, L. Jin, W. Wu, S. X.-D. Tan, and J. Yang, –Fast thermal simulation for architecture level dynamic thermal management, — in Proc. Int. Conf. on Computer Aided Design (ICCAD), Nov 2005, 639-644.
-
(2005)
Proc. Int. Conf. on Computer Aided Design (ICCAD)
, pp. 639-644
-
-
Liu, P.1
Qi, Z.2
Li, H.3
Jin, L.4
Wu, W.5
Tan, S.X.6
Yang, J.7
-
75
-
-
33751428898
-
An efficient method for terminal reduction of interconnect circuits considering delay variations
-
P. Liu, S. X.-D. Tan, H. Li, Z. Qi, J. Kong, B. McGaughy, and L. He, –An efficient method for terminal reduction of interconnect circuits considering delay variations, — in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2005, 821-826.
-
(2005)
Proc. Int. Conf. on Computer Aided Design (ICCAD)
, pp. 821-826
-
-
Liu, P.1
Tan, S.X.2
Li, H.3
Qi, Z.4
Kong, J.5
McGaughy, B.6
He, L.7
-
76
-
-
34548139994
-
Compact reduced order modeling for multiple-port interconnects
-
P. Liu, S. X.-D. Tan, B. McGaughy, and L. Wu, –Compact reduced order modeling for multiple-port interconnects, — in Proc. Int. Symposium. on Quality Electronic Design (ISQED), 2006, 413-418.
-
(2006)
Proc. Int. Symposium. on Quality Electronic Design (ISQED)
, pp. 413-418
-
-
Liu, P.1
Tan, S.X.2
McGaughy, B.3
Wu, L.4
-
78
-
-
0033363574
-
Full-wave modeling and automatic equivalent-circuit generation of millimeter-wave planar and multilayer structures
-
June
-
T. Mangold and P. Russer, –Full-wave modeling and automatic equivalent-circuit generation of millimeter-wave planar and multilayer structures, — IEEE Trans. on Microwave Theory and Techniques, 47, (6), 851-858, June 1999.
-
(1999)
IEEE Trans. on Microwave Theory and Techniques
, vol.47
, Issue.6
, pp. 851-858
-
-
Mangold, T.1
Russer, P.2
-
79
-
-
0036625314
-
Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit crosstalk
-
Y. Massoud and J. White, –Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit crosstalk, — IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 2002.
-
(2002)
IEEE Trans. on Very Large Scale Integration (VLSI) Systems
-
-
Massoud, Y.1
White, J.2
-
80
-
-
0000781311
-
Computeraided circuit analysis tools for rfic simulation: Algorithms, features, and limitations
-
K. Mayaram, D. C. Lee, S. Moinian, D. R. Rich, and J. Joychowdhury, –Computeraided circuit analysis tools for RFIC simulation: algorithms, features, and limitations, — IEEE Trans. on Circuits and Systems II: analog and digital signal processing, 47, (4), 274-286, 2000.
-
(2000)
IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing
, vol.47
, Issue.4
, pp. 274-286
-
-
Mayaram, K.1
Lee, D.C.2
Moinian, S.3
Rich, D.R.4
Joychowdhury, J.5
-
81
-
-
0019533482
-
Principle component analysis in linear systems: Controllability, and observability, and model reduction
-
B. Moore, –Principle component analysis in linear systems: Controllability, and observability, and model reduction, — IEEE Trans. Automat. Contr., 26, (1), 17-32, 1981.
-
(1981)
IEEE Trans. Automat. Contr
, vol.26
, Issue.1
, pp. 17-32
-
-
Moore, B.1
-
83
-
-
0026255002
-
Fastcap: A multipole accelerated 3d capacitance extraction program
-
K. Narbos and J. White, –FastCap: a multipole accelerated 3D capacitance extraction program, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 10, (11), 1447-1459, 1991.
-
(1991)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.10
, Issue.11
, pp. 1447-1459
-
-
Narbos, K.1
White, J.2
-
84
-
-
0034823548
-
Analysis of eddy current losses over conductive substrates with applications to monolithic inductors and transformers
-
Jan
-
A. M. Niknejad and R. G. Meyer, –Analysis of eddy current losses over conductive substrates with applications to monolithic inductors and transformers, — IEEE Trans. on Microwave Theory and Techniques, 166-76, Jan. 2001.
-
(2001)
IEEE Trans. on Microwave Theory and Techniques
, pp. 166-176
-
-
Niknejad, A.M.1
Meyer, R.G.2
-
85
-
-
0032139262
-
Prima: Passive reduced-order interconnect macromodeling algorithm
-
A. Odabasioglu, M. Celik, and L. Pileggi, –PRIMA: Passive reduced-order interconnect macromodeling algorithm, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 645-654, 1998.
-
(1998)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, pp. 645-654
-
-
Odabasioglu, A.1
Celik, M.2
Pileggi, L.3
-
87
-
-
0036056697
-
Guaranteed passive balancing transformations for model order reduction
-
J. R. Phillips, L. Daniel, and L. M. Silveira, –Guaranteed passive balancing transformations for model order reduction, — in Proc. Design Automation Conf. (DAC), 2002, 52-57.
-
(2002)
Proc. Design Automation Conf. (DAC)
, pp. 52-57
-
-
Phillips, J.R.1
Daniel, L.2
Silveira, L.M.3
-
88
-
-
0042594367
-
Guaranteed passive balanced transformation for model order reduction
-
J. R. Phillips, L. Daniel, and L. M. Silveira, –Guaranteed passive balanced transformation for model order reduction, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 22, (8), 1027-1041, 2003.
-
(2003)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.22
, Issue.8
, pp. 1027-1041
-
-
Phillips, J.R.1
Daniel, L.2
Silveira, L.M.3
-
90
-
-
11844291283
-
Poor man's tbr: A simple model reduction scheme
-
J. R. Phillips and L. M. Silveira, –Poor man's TBR: a simple model reduction scheme, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 24, (1), 43-55, 2005.
-
(2005)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.24
, Issue.1
, pp. 43-55
-
-
Phillips, J.R.1
Silveira, L.M.2
-
93
-
-
33746660607
-
Wideband modeling of rf/analog circuits via hierarchical multi-point model order reduction
-
Jan
-
Z. Qi, S. X.-D. Tan, H. Yu, L. He, and P. Liu, –Wideband modeling of RF/analog circuits via hierarchical multi-point model order reduction, — in Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Jan. 2005, 224-229.
-
(2005)
Proc. Asia South Pacific Design Automation Conf. (ASPDAC)
, pp. 224-229
-
-
Qi, Z.1
Tan, S.X.2
Yu, H.3
He, L.4
Liu, P.5
-
94
-
-
33746626527
-
Wideband passive multi-port model order reduction and realization of rlcm circuits
-
Aug
-
Z. Qi, H. Yu, P. Liu, S. X.-D. Tan, and L. He, –Wideband passive multi-port model order reduction and realization of RLCM circuits, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 1496-1509, Aug. 2006.
-
(2006)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, pp. 1496-1509
-
-
Qi, Z.1
Yu, H.2
Liu, P.3
Tan, S.X.4
He, L.5
-
95
-
-
23744444927
-
Power grid analysis using random walks
-
H. Qian, S. Nassif, and S. Sapatnekar, –Power grid analysis using random walks, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 1204-1224, 2005.
-
(2005)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, pp. 1204-1224
-
-
Qian, H.1
Nassif, S.2
Sapatnekar, S.3
-
98
-
-
0042635847
-
Realizable parasitic reduction using generalized y-transformation
-
Z. Qin and C. Cheng, –Realizable parasitic reduction using generalized Y-transformation, — in Proc. Design Automation Conf. (DAC), 2003, 220-225.
-
(2003)
Proc. Design Automation Conf. (DAC)
, pp. 220-225
-
-
Qin, Z.1
Cheng, C.2
-
100
-
-
0020778211
-
Signal delay in rc tree networks
-
J. Rubinstein, P. Penfield, and M. A. Horowitz, –Signal delay in RC tree networks, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 202-211, 1983.
-
(1983)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, pp. 202-211
-
-
Rubinstein, J.1
Penfield, P.2
Horowitz, M.A.3
-
101
-
-
0016035432
-
Equivalent circuits models for three dimensional multiconductor systems
-
A. E. Ruehli, –Equivalent circuits models for three dimensional multiconductor systems, — IEEE Trans. on Microwave Theory and Techniques, 216-220, 1974.
-
(1974)
IEEE Trans. on Microwave Theory and Techniques
, pp. 216-220
-
-
Ruehli, A.E.1
-
103
-
-
0031357998
-
An explicit method for computing the positive real lemma matrices
-
N. Sadegh, J. D. Finney, and B. S. Heck, –An explicit method for computing the positive real lemma matrices, — Int. J. Robust and Nonlinear Control, 7, 1057-1069, 1997.
-
(1997)
Int. J. Robust and Nonlinear Control
, vol.7
, pp. 1057-1069
-
-
Sadegh, N.1
Finney, J.D.2
Heck, B.S.3
-
104
-
-
18844414120
-
-
Institute of Automation, University of Bremen, Tech. Rep., Aug
-
B. Salimbahrami and B. Lohmann, –Krylov subspace methods in linear model order reduction: introduction and invariance properties, — Institute of Automation, University of Bremen, Tech. Rep., Aug. 2002.
-
(2002)
–Krylov Subspace Methods in Linear Model Order Reduction: Introduction and Invariance Properties
-
-
Salimbahrami, B.1
Lohmann, B.2
-
105
-
-
2442417853
-
A fast algorithm and practical considerations for passive macromodeling of measured/simulated data
-
Feb
-
D. Saraswat, R. Achar, and M. Nakhla, –A fast algorithm and practical considerations for passive macromodeling of measured/simulated data, — IEEE Trans. on Advanced Packaging, 27, (1), 57-70, Feb. 2004.
-
(2004)
IEEE Trans. on Advanced Packaging
, vol.27
, Issue.1
, pp. 57-70
-
-
Saraswat, D.1
Achar, R.2
Nakhla, M.3
-
106
-
-
0016481606
-
Fast and accurate switching transient calculations on transmission lines with ground return using recursive convolution
-
A. Semlyen and A. Dabuleanu, –Fast and accurate switching transient calculations on transmission lines with ground return using recursive convolution, — IEEE Trans. Power Apparatus and Systems, 94, (2), 1975.
-
(1975)
IEEE Trans. Power Apparatus and Systems
, vol.94
, Issue.2
-
-
Semlyen, A.1
Dabuleanu, A.2
-
109
-
-
0001144063
-
Return-limited inductances: A practical approach to onchip inductance extraction
-
K. Shepard and Z. Tian, –Return-limited inductances: A practical approach to onchip inductance extraction, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 19, (4), 425-436, 2000.
-
(2000)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.19
, Issue.4
, pp. 425-436
-
-
Shepard, K.1
Tian, Z.2
-
110
-
-
0033882369
-
Canonical symbolic analysis of large analog circuits with determinant decision diagrams
-
Jan
-
C.-J. Shi and X.-D. Tan, –Canonical symbolic analysis of large analog circuits with determinant decision diagrams, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 19, (1), 1-18, Jan. 2000.
-
(2000)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.19
, Issue.1
, pp. 1-18
-
-
Shi, C.-J.1
Tan, X.-D.2
-
111
-
-
0035398370
-
Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design
-
April
-
C.-J. Shi and X.-D. Tan, –Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 20, (7), 813-827, April 2001.
-
(2001)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.20
, Issue.7
, pp. 813-827
-
-
Shi, C.-J.1
Tan, X.-D.2
-
112
-
-
85025616505
-
Samson: A generalized second-order arnoldi mehtod for multi-source network reduction
-
Y. Shi, H. Yu, and L. He, –SAMSON: a generalized second-order Arnoldi mehtod for multi-source network reduction, — in Proc. ACM Int. Symp. on Physical Design (ISPD), 2006.
-
(2006)
Proc. ACM Int. Symp. on Physical Design (ISPD)
-
-
Shi, Y.1
Yu, H.2
He, L.3
-
113
-
-
0030387972
-
A coordinate-transformed arnoldi algorithm for generating guaranteed stable reduced-order models of rlc circuits
-
M. Silveira, M. Kamon, I. Elfadel, and J. White, –A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits, — in Proc. Int. Conf. on Computer Aided Design (ICCAD), 1996, 288-294.
-
(1996)
Proc. Int. Conf. on Computer Aided Design (ICCAD)
, pp. 288-294
-
-
Silveira, M.1
Kamon, M.2
Elfadel, I.3
White, J.4
-
114
-
-
0029237866
-
Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-d interconnect structures
-
June
-
M. Silveira, M. Kamon, and J. White, –Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures, — in Proc. Design Automation Conf. (DAC), June 1995, 376-380.
-
(1995)
Proc. Design Automation Conf. (DAC)
, pp. 376-380
-
-
Silveira, M.1
Kamon, M.2
White, J.3
-
117
-
-
0022688734
-
Flowgraph analysis of large electronic networks
-
March
-
J. A. Starzky and A. Konczykowska, –Flowgraph analysis of large electronic networks, — IEEE Trans. on Circuits and Systems, 33, (3), 302-315, March 1986.
-
(1986)
IEEE Trans. on Circuits and Systems
, vol.33
, Issue.3
, pp. 302-315
-
-
Starzky, J.A.1
Konczykowska, A.2
-
118
-
-
0033296299
-
Using sudumi 1.02, a matlab toolbox for optimization over symmetric cones
-
J. Sturm, –Using SuDuMi 1.02, a MATLAB toolbox for optimization over symmetric cones, — Optim. Meth. Softw., 10, 625-653, 1999.
-
(1999)
Optim. Meth. Softw
, vol.10
, pp. 625-653
-
-
Sturm, J.1
-
119
-
-
2342512219
-
Gramian-based model order reduction for descriptor systems
-
T. Stykel, –Gramian-based model order reduction for descriptor systems, — Math. Control Signals Systems, 16, 297-319, 2004.
-
(2004)
Math. Control Signals Systems
, vol.16
, pp. 297-319
-
-
Stykel, T.1
-
120
-
-
0344089095
-
Optimal decoupling capacitor sizing and placement for standard cell layout designs
-
April
-
H. Su, S. S. Sapatnekar, and S. R. Nassif, –Optimal decoupling capacitor sizing and placement for standard cell layout designs, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 22, (4), 428-436, April 2003.
-
(2003)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.22
, Issue.4
, pp. 428-436
-
-
Su, H.1
Sapatnekar, S.S.2
Nassif, S.R.3
-
121
-
-
0347409183
-
A general s-domain hierarchical network reduction algorithm
-
S. X.-D. Tan, –A general s-domain hierarchical network reduction algorithm, — in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2003, 650-657.
-
(2003)
Proc. Int. Conf. on Computer Aided Design (ICCAD)
, pp. 650-657
-
-
Tan, S.X.1
-
123
-
-
4444375918
-
Hierarchical approach to exact symbolic analysis of large analog circuits
-
June
-
S. X.-D. Tan, W. Guo, and Z. Qi, –Hierarchical approach to exact symbolic analysis of large analog circuits, — in Proc. Design Automation Conf. (DAC), June 2004, 860-863.
-
(2004)
Proc. Design Automation Conf. (DAC)
, pp. 860-863
-
-
Tan, S.X.1
Guo, W.2
Qi, Z.3
-
124
-
-
3042611748
-
Hierarchical modeling and simulation of large analog circuits
-
Feb
-
S. X.-D. Tan, Z. Qi, and H. Li, –Hierarchical modeling and simulation of large analog circuits, — in Proc. European Design and Test Conf. (DATE), Feb. 2004, 740-741.
-
(2004)
Proc. European Design and Test Conf. (DATE)
, pp. 740-741
-
-
Tan, S.X.1
Qi, Z.2
Li, H.3
-
125
-
-
4344690084
-
Hurwitz stable model reduction for non-tree structured rlck circuits
-
S. X.-D. Tan and J. Yang, –Hurwitz stable model reduction for non-tree structured RLCK circuits, — in IEEE Int. System-on-Chip Conf. (SOC), 2003, 239-242.
-
(2003)
IEEE Int. System-On-Chip Conf. (SOC)
, pp. 239-242
-
-
Tan, S.X.1
Yang, J.2
-
126
-
-
0003119486
-
Hierarchical symbolic analysis of large analog circuits via determinant decision diagrams
-
April
-
X.-D. Tan and C.-J. Shi, –Hierarchical symbolic analysis of large analog circuits via determinant decision diagrams, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 19, (4), 401-412, April 2000.
-
(2000)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.19
, Issue.4
, pp. 401-412
-
-
Tan, X.-D.1
Shi, C.-J.2
-
130
-
-
0033684005
-
Extended krylov subspace method for reduced order analysis of linear circuit with multiple sources
-
J. M. Wang and T. V. Nguyen, –Extended Krylov subspace method for reduced order analysis of linear circuit with multiple sources, — in Proc. Design Automation Conf. (DAC), 2003, 247-252.
-
(2003)
Proc. Design Automation Conf. (DAC)
, pp. 247-252
-
-
Wang, J.M.1
Nguyen, T.V.2
-
131
-
-
33751423834
-
Fast balanced stochastic truncation via a quadratic extension of the alternating direction implicit iteration
-
N. Wang and V. Balakrishnan, –Fast balanced stochastic truncation via a quadratic extension of the alternating direction implicit iteration, — in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2005, 801-805.
-
(2005)
Proc. Int. Conf. on Computer Aided Design (ICCAD)
, pp. 801-805
-
-
Wang, N.1
Balakrishnan, V.2
-
132
-
-
0022082468
-
Waveform relaxation: Theory and practice
-
J. White, F. Odeh, A. Sangiovanni-Vincentelli, and A. Ruehli, –Waveform relaxation: theory and practice, — Trans. Soc. Compu. Simul., 95-133, 1985.
-
(1985)
Trans. Soc. Compu. Simul
, pp. 95-133
-
-
White, J.1
Odeh, F.2
Sangiovanni-Vincentelli, A.3
Ruehli, A.4
-
134
-
-
0041633619
-
Vector potential equivalent circuit based on peec inversion
-
H. Yu and L. He, –Vector potential equivalent circuit based on PEEC inversion, — in Proc. Design Automation Conf. (DAC), 2003, 781-723.
-
(2003)
Proc. Design Automation Conf. (DAC)
, pp. 723-781
-
-
Yu, H.1
He, L.2
-
135
-
-
23744433491
-
A provably passive and cost-efficient model for inductive interconnects
-
H. Yu and L. He, –A provably passive and cost-efficient model for inductive interconnects, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 24, (8), 1283-1294, 2005.
-
(2005)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.24
, Issue.8
, pp. 1283-1294
-
-
Yu, H.1
He, L.2
-
136
-
-
34548132219
-
Block structure preserving model reduction for linear circuits with large numbers of ports
-
H. Yu, L. He, and S. X. D. Tan, –Block structure preserving model reduction for linear circuits with large numbers of ports, — in Proc. IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), 2005, 1-6.
-
(2005)
Proc. IEEE International Workshop on Behavioral Modeling and Simulation (BMAS)
, pp. 1-6
-
-
Yu, H.1
He, L.2
Tan, S.X.3
-
137
-
-
20344382958
-
Compact macro-modeling for on-chip rf passive components
-
H. Yu, L. He, and S. X.-D. Tan, –Compact macro-modeling for on-chip RF passive components, — in Proc. IEEE International Conference on Communications, Circuits and Systems, 2004, 199-202.
-
(2004)
Proc. IEEE International Conference on Communications, Circuits and Systems
, pp. 199-202
-
-
Yu, H.1
He, L.2
Tan, S.X.3
-
138
-
-
34547208343
-
Fast analysis of structured power grid by triangularization based structure preserving model order reduction
-
H. Yu, Y. Shi, and L. He, –Fast analysis of structured power grid by triangularization based structure preserving model order reduction, — in Proc. Design Automation Conf. (DAC), 2006, 205-210.
-
(2006)
Proc. Design Automation Conf. (DAC)
, pp. 205-210
-
-
Yu, H.1
Shi, Y.2
He, L.3
-
139
-
-
0036474411
-
Hierarchical analysis of power distribution networks
-
Feb
-
M. Zhao, R. V. Panda, S. S. Sapatnekar, and D. Blaauw, –Hierarchical analysis of power distribution networks, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 21, (2), 159-168, Feb. 2002.
-
(2002)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.21
, Issue.2
, pp. 159-168
-
-
Zhao, M.1
Panda, R.V.2
Sapatnekar, S.S.3
Blaauw, D.4
-
140
-
-
0036911692
-
On-chip interconnect modeling by wire duplication
-
G. Zhong, C. Koh, and K. Roy, –On-chip interconnect modeling by wire duplication, — in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2002, 341-346.
-
(2002)
Proc. Int. Conf. on Computer Aided Design (ICCAD)
, pp. 341-346
-
-
Zhong, G.1
Koh, C.2
Roy, K.3
-
141
-
-
0242551588
-
On-chip interconnect modeling by wire duplication
-
G. Zhong, C. Koh, and K. Roy, –On-chip interconnect modeling by wire duplication, — IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 22, (11), 1521-1532, 2003.
-
(2003)
IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems
, vol.22
, Issue.11
, pp. 1521-1532
-
-
Zhong, G.1
Koh, C.2
Roy, K.3
|