On-chip interconnect modeling by wire duplication

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 341-346

  Zhong, Guoan ^a   Koh, Cheng Kok ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INDUCTANCE MATRIX; INTERCONNECT MODELING TECHNIQUE;

COMPUTER SIMULATION; EQUIVALENT CIRCUITS; INDUCTANCE; INVERSE PROBLEMS; MATHEMATICAL MODELS; MATRIX ALGEBRA;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036911692     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774623     Document Type: Conference Paper

References (8)

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8. G. Zhong, C.-K. Koh, and K. Roy. On-chip interconnect modeling by wire duplication In Purdue University Technical Report, ECE-02-04, 2002.