-
1
-
-
0043136760
-
Realizable RLCK circuit crunching
-
C. S. Amin, M. H. Chowdhury, and Y. I. Ismail, "Realizable RLCK circuit crunching" in Proc: Design Automation Conf. (DAC), 2003, pp, 226-231
-
(2003)
Proc: Design Automation Conf. (DAC)
, pp. 226-231
-
-
Amin, C.S.1
Chowdhury, M.H.2
Ismail, Y.I.3
-
2
-
-
1242308409
-
A convex programming approach for generating guaranteed passive approximations to tabulated frequency-data
-
Feb.
-
J. P. C. P. Coelho and L. M. Silveira, "A convex programming approach for generating guaranteed passive approximations to tabulated frequency-data," IEEE Trans, an Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 2, pp. 293-301, Feb. 2004.
-
(2004)
IEEE Trans, An Computer-Aided Design of Integrated Circuits and Systems
, vol.23
, Issue.2
, pp. 293-301
-
-
Coelho, J.P.C.P.1
Silveira, L.M.2
-
3
-
-
0029250497
-
Analysis of interconnect networks using complex frequency hopping
-
Feb.
-
E. Chiprout and M. S. Nakhla, "Analysis of interconnect networks using complex frequency hopping," IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-14, no. 2, pp. 186-200, Feb. 1995.
-
(1995)
IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems
, vol.CAD-14
, Issue.2
, pp. 186-200
-
-
Chiprout, E.1
Nakhla, M.S.2
-
4
-
-
0029735239
-
Including higher-order moments of RC interconnections in layout-to-circuit extraction
-
P. Elias and N. van der Meijs, "Including higher-order moments of RC interconnections in layout-to-circuit extraction," in Proc. European Design and Test Conf (DATE), 1996, pp. 362-366.
-
(1996)
Proc. European Design and Test Conf (DATE)
, pp. 362-366
-
-
Elias, P.1
Van Der Meijs, N.2
-
5
-
-
0029308198
-
Efficient linear circuit analysis by Dade approximation via the lanczos process
-
May
-
P. Feldmann and R. W. Freund, "Efficient linear circuit analysis by Dade approximation via the lanczos process," IEEE Trans, on Computer-Aided Design of integrated Circuits and Systems, vol. 14, no. 5, pp, 639-649, May 1995.
-
(1995)
IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems
, vol.14
, Issue.5
, pp. 639-649
-
-
Feldmann, P.1
Freund, R.W.2
-
6
-
-
0030397409
-
Reduced-order modeling of large linear subcircuits by means of the sypvl algorithm
-
R. W. Freund and P. Feldmann, "Reduced-order modeling of large linear subcircuits by means of the sypvl algorithm," in Proc. InL Conf. on Computer Aided Design (ICCAD), 1996, pp. 280-287.
-
(1996)
Proc. InL Conf. on Computer Aided Design (ICCAD)
, pp. 280-287
-
-
Freund, R.W.1
Feldmann, P.2
-
7
-
-
0000195442
-
Computer-aided design of analog and mixed-signal integrated circuits
-
Dec.
-
G. Gielen and R. Rutenbar, "Computer-aided design of analog and mixed-signal integrated circuits" Proc. of IEEE, vol. 88, no. 12, pp. 703-717, Dec. 2000
-
(2000)
Proc. of IEEE
, vol.88
, Issue.12
, pp. 703-717
-
-
Gielen, G.1
Rutenbar, R.2
-
8
-
-
0029288199
-
A hierarchical network approach to symbolic analysis oflarge scale networks
-
April
-
M. M. Hassoun and P. M. Lin, "A hierarchical network approach to symbolic analysis oflarge scale networks," IEEE Trans, on Circuits ana Systems I: Fundamental Theory and Applications, vol. 42, no. 4, pp. 201-211, April 1995.
-
(1995)
IEEE Trans, on Circuits Ana Systems I: Fundamental Theory and Applications
, vol.42
, Issue.4
, pp. 201-211
-
-
Hassoun, M.M.1
Lin, P.M.2
-
10
-
-
0036474096
-
DTT: Direct truncation of the transfer function -an alternative to moment matching for tree structured interconnect
-
Feb.
-
Y. Ismail and E. G. Friedman, "DTT: direct truncation of the transfer function -an alternative to moment matching for tree structured interconnect," IEEE Trans, an Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 2, pp. 131-144, Feb. 2003.
-
(2003)
IEEE Trans, An Computer-Aided Design of Integrated Circuits and Systems
, vol.21
, Issue.2
, pp. 131-144
-
-
Ismail, Y.1
Friedman, E.G.2
-
11
-
-
0028498583
-
FastHeory: A multipole-accelerated 3D inductance extraction program
-
Sept.
-
M. Kamon, M. Tsuk, and JrWhite, "FastHeory: a multipole-accelerated 3D inductance extraction program," IEEE Trans, on Microwave Theory and Techniques, pp. 1750-1758, Sept 1994.
-
(1994)
IEEE Trans, on Microwave Theory and Techniques
, pp. 1750-1758
-
-
Kamon, M.1
Tsuk, M.2
White, Jr.3
-
14
-
-
0033363574
-
Full-wave modeling and automatic equivalent-circuit generation of millimeter-wave planar and multilayer structures
-
June
-
T. Mangold and P. Russer, "Full-wave modeling and automatic equivalent-circuit generation of millimeter-wave planar and multilayer structures," IEEE Trans, on Microwave Theory and Techniques, vol. 47, no. 6, pp. 851-858, June 1999.
-
(1999)
IEEE Trans, on Microwave Theory and Techniques
, vol.47
, Issue.6
, pp. 851-858
-
-
Mangold, T.1
Russer, P.2
-
15
-
-
0036625314
-
Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit crosstalk
-
Y. Massoud and J. White, "Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit crosstalk," IEEE Trans, on Very Large Scale Integration (VLSI) Systems, 2002.
-
(2002)
IEEE Trans, on Very Large Scale Integration (VLSI) Systems
-
-
Massoud, Y.1
White, J.2
-
16
-
-
0026255002
-
FastCap: A multipole accelerated 3D capacitance extraction program
-
K. Narbos and J. White, "FastCap: A multipole accelerated 3D capacitance extraction program," IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 11, pp. 1447-1459, 1991
-
(1991)
IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems
, vol.10
, Issue.11
, pp. 1447-1459
-
-
Narbos, K.1
White, J.2
-
17
-
-
0032139262
-
PRIMA: Passive reduced-order interconnect macromodeling algorithm
-
A. Odabasioglu, M. Celik, and L. Pileggi, "PRIMA: Passive reduced-order interconnect macromodeling algorithm," IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, pp. 645-654, 1995.
-
(1995)
IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems
, pp. 645-654
-
-
Odabasioglu, A.1
Celik, M.2
Pileggi, L.3
-
20
-
-
0042635847
-
Realizable parasitic reduction using generalized y - Δ transformation
-
Z. Qin and C. Cheng, "Realizable parasitic reduction using generalized Y - Δ transformation," in Proc. Design Automation Conf. (DAC), 2003, pp. 220-225.
-
(2003)
Proc. Design Automation Conf. (DAC)
, pp. 220-225
-
-
Qin, Z.1
Cheng, C.2
-
22
-
-
0016035432
-
Equivalent circuits models for three dimensional muldconductor systems
-
A, E. Ruetili, "Equivalent circuits models for three dimensional muldconductor systems," IEEE Trans, on Microwave Theory and Techniques, pp. 216-220, 1974.
-
(1974)
IEEE Trans, on Microwave Theory and Techniques
, pp. 216-220
-
-
Ruetili, A.E.1
-
25
-
-
0033882369
-
Canonical symbolic analysis of large analog circuits with determinant decision diagrams
-
Jan.
-
C.-J. Shi and X.-D. Tan, "Canonical symbolic analysis of large analog circuits with determinant decision diagrams," IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 1,pp. 1-18, Jan. 2000.
-
(2000)
IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems
, vol.19
, Issue.1
, pp. 1-18
-
-
Shi, C.-J.1
Tan, X.-D.2
-
26
-
-
0022688734
-
Flowgraph analysis of large electronic nei-works
-
March
-
J. A. Starzky and A. Konczykowska, "Flowgraph analysis of large electronic nei-works," IEEE Trans, on Circuits and Systems I: Fundamental Theory and Applications, vol. 33, no. 3, pp. 302-315, March 1986.
-
(1986)
IEEE Trans, on Circuits and Systems I: Fundamental Theory and Applications
, vol.33
, Issue.3
, pp. 302-315
-
-
Starzky, J.A.1
Konczykowska, A.2
-
28
-
-
3042611748
-
Hierarchical modeling and simulation of large analog circuits
-
Feb.
-
S. X.-D. Tan, Z. Qi, and H. Li, "Hierarchical modeling and simulation of large analog circuits," in Proc. European Design and Test Conf. (DATE), Feb, 2004, pp, 740-741.
-
(2004)
Proc. European Design and Test Conf. (DATE)
, pp. 740-741
-
-
Tan, S.X.-D.1
Qi, Z.2
Li, H.3
-
29
-
-
0003119486
-
Hierarchical symboHc analysis of large analog circuits via determinant decision diagrams
-
April
-
X.-D. Tan and C.-J. Shi, "Hierarchical symboHc analysis of large analog circuits via determinant decision diagrams," IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 4, pp. 401-412, April 2000.
-
(2000)
IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems
, vol.19
, Issue.4
, pp. 401-412
-
-
Tan, X.-D.1
Shi, C.-J.2
-
31
-
-
0041633619
-
Vector potential equivalent circuit based on PEEC inversion
-
H. Yu and L. He, "Vector potential equivalent circuit based on PEEC inversion," in Proc. Design Automation Conf. (DAC), 2003, pp. 781-723.
-
(2003)
Proc. Design Automation Conf. (DAC)
, pp. 781-723
-
-
Yu, H.1
He, L.2
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