Symbolic analysis and reduction of VLSI circuits

Symbolic Analysis and Reduction of VLSI Circuits

Volumn , Issue , 2005, Pages 1-283

  Qin, Zhanhai ^a   Tan, Sheldon X D ^a   Cheng, Chung Kuan ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84891454234     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/b103124     Document Type: Book

References (108)

1. S. B. Akers, "Binary decision diagrams", IEEE Trans, on Computers, vol. 27, no. 6, pp. 509-516, 1976.
2. C. S. Amin, M. H. Chowdhury, and Y. I. Ismail, 'Realizable rick circuit crunching", in Proc. Design Automation Conf. (DAC), 2003, pp. 226-231.
3. R. I. Bahar, E. A. Frohm, C. M. Gaona, G. A. Hachtel, E. Macii, A. Pardo, and F. Somenzi, 'Algebraic decision diagrams and their applications", in Proc. Int. Conf. on Computer Aided Design (ICCAD), Nov. 1993, pp. 188-191.
4. R. E. Bryant, 'Graph-based algorithms for Boolean function manipulation", IEEE Trans. on Computers, pp. 677-691, 1986.
5. - "Binary decision diagrams and beyond: enabling technologies for formal veriflcation", in Proc. Int. Conf. on Computer Aided Design (ICCAD), 1995.
6. R. E. Bryant and Y. A. Chen, "Verification of arithmetic functions with binary moment diagrams", in Proc. Design Automation Conf. (DAC), 1995, pp. 535-541.
7. R. Carmassi, M. Catelani, G. Iuculano, A. Liberatore, S. Manetti, and M. Marini, "Analog network testability measurement: a symbolic formulation approach", IEEE Trans. Instrumentation and Measurement, vol. 40, pp. 930-935, Dec. 1991.
8. S.-M. Chang, J.-F. MacKey, and G. M. Wierzba, "Matrix reduction and numerical approximation during computation techniques for symbolic analog circuit analysis", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 1992, pp. 1153-1156.
9. H. Chapellat, M. Mansour, and S. P. Bhattacharyya, "Elementary proofs of some classical stability criteria", IEEE transations on education, vol. 33, pp. 232-239, 1990.
10. B. W. Char and et al, Maple V: Language Reference Manual. Springer-Verlag, 1991.
11. W. K. Chen, "Topological analysis for active networks", IEEE Trans. Circuit Theory, vol. CT-12, pp. 85-91, Mar. 1965.
12. - Applied Graph Theory: Graphs and Electrical Networks. New York: American Elsevier, 1976.
13. E. M. Clarke, M. Fujita, and X. Zhao, Multi-terminal binary decision diagrams and hybrid decision diagrams. Kluwer Academic Publishers, 1996, ch. 4 in book "Representations of Discrete Functions", pp. 93-108.
14. C. L. Coates, "Flow-graph solutions of linear algebraic equations", IRE transactions on circuit theory, vol. CT-6, pp. 170-187, 1959.
15. C. P. Coelho, J. R. Phillips, and L. M. Silveira, "A new proof of the Routh-Hurwitz stability criterion using the second method of Lyapunov", in Proceedings of Cambridge philosophy society meeting, vol. 58, Nov. 1962, pp. 694-702.
16. J. Cong, L. He, C.-K. Koh, and P. Padden, "Performance optimization of VLSI interconnect layout", Integration, the VLSI Journal, vol. 21, no. 1 & 2, pp. 1-94, Nov. 1996.
17. T. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to Algorithms. Cambridge, Massachusetts: The MIT Press, 1990.
18. W. Daems, G. Gielen, and W. Sansen, "Circuit simplification for the symbolic analysis of analog integrated circuits", IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 4, pp. 395-407, April 2002.
19. W. Daems, W. Verhaegen, P. Wambacq, G. Gielen, and W. Sansen, "Evaluation of errorcontrol strategies for the linear symbolic analysis of analog integrated circuits", IEEE Trans, on Circuits and Systems I: Fundamental Theory and Applications, vol. 46, no. 5, pp. 594-606, May 1999.
20. A. Devgan, H. Ji, and W. Dai, "How to efficiently capture on-chip inductance effects: introducing a new circuit element K", in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2000, pp. 150-155.
21. R. J. Duffin, E. L. Peterson, and C. Zener, Geometric programming-theory and application. New York: John Wiley & Sons, Inc., 1967.
22. P. Elias and N. van der Meijs, "Including higher-order moments of RC interconnections in layout-to-circuit extraction", in Proc. European Design and Test Conf. (DATE), 1996, pp. 362-366.
23. P. Feldmann and R. W. Freund, "Efficient linear circuit analysis by pade approximation via the lanczos process", IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 5, pp. 639-649, May 1995.
24. - "Reduced-order modeling of large linear subcircuits via block lanczos algorithm", in Proc. Design Automation Conf. (DAC), 1995, pp. 376-380.
25. "Reduced-order modeling of large linear subcircuits by means of the sypvl algorithm", in Proc. Int. Conf. on Computer Aided Design (ICCAD), 1996, pp. 280-287.
26. A. Feliachi, "Control systems curriculum national survey", IEEE Transactions on education, pp. 257-263, Aug. 1994.
27. F. V. Fernández, J. Martín, A. Rodríguez- Vázquez, and J. L. Huertas, "On simplification techniques for symbolic analysis of analog integrated circuits, "in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 1992, pp. 1149-1152.
28. F. V. Fernández and A. Rodríguez-Vázquez, "Symbolic analysis tools-the state of the art", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 1996, pp. 798-801.
29. F. V. Fernández, A. Rodríguez-Vázquez, J. L. Hertas, and G. Gielen, Symbolic Analysis Techniques: Application to Analog Design Automation. IEEE Press, 1998.
30. F. V, Fernández, P. Wambacq, G. Gielen, A. Rodríguez- Vázquez, and W. Sansen, "Symbolic analysis of large analog integrated circuits by approximation during expression generation", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 1994, pp. 25-28.
31. H. Floberg, Symbolic Analysis in Analog Integrated Circuit Design. Massachusetts: Kluwer Academic Publisher, 1997.
32. G. E. Forsythe, M. A. Malcolm, and C. B. Moller, Computer methods for mathematical computations. Prentice-Hall, 1977.
33. F. R. Gantmacher, The theory of matrices. New York: Chelsea Pub. Co., 1959, vol. II.
34. - The Theory of Matrices, Vol. 1. New York: Chelsea Pub. Co., 1977.
35. A. George and J. W. Liu, Computer solution of large sparse positive deft nite systems. Englewood Cliffs, NJ: Prentice-Hall, 1981.
36. G. Gielen and R. Rutenbar, "Computer-aided design of analog and mixed-signal integrated circuits", Proc. of IEEE, vol. 88, no. 12, pp. 703-717, Dec. 2000.
37. G. Gielen and W. Sansen, Symbolic Analysis for Automated Design of Analog Integrated Circuits. Kluwer Academic Publishers, 1991.
38. G. Gielen, P. Wambacq, and W. Sansen, "Symbolic analysis methods and applications for analog circuits: A tutorial overview", Proc. of IEEE, vol. 82, no. 2, pp. 287-304, Feb. 1994.
39. E. A. Guillemin, The mathematics of circuit analysis; extensions to the mathematical training of electrical engineers, Principles of electrical engineering series. New York: J. Wiley, 1949.
40. M. M. Hassoun and P. M. Lin, "A new network approach to symbolic simulation of large-scale network", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 1989, pp. 806-809.
41. -' 'A hierarchical network approach to symbolic analysis of large scale networks", IEEE Trans, on Circuits and Systems I: Fundamental Theory and Applications, vol. 42, no. 4, pp. 201-211, April 1995.
42. J.-J. Hsu and C. Sechen, "DC small signal symbolic analysis of large analog integrated circuits", IEEE Trans, on Circuits and Systems I: Fundamental Theory and Applications, vol. 41, no. 12, pp. 817-828, Dec. 1994.
43. Y. Ismail and E. G. Friedman, "DTT: direct truncation of the transfer function - an alternative to moment matching for tree structured interconnect", IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 2, pp. 131-144, Feb. 2003.
44. H. Ji, A. Devgan, and W. Dai, "Ksim: A stable and efficient RKC simulator for capturing on-chip inductance effect", in Proc. Asia South Pacific Design Automation Conf. (ASPDAC), 2001, pp. 379-384.
45. R. L. R. K. S. Brace and R. E. Byrant, "Efficient implementation of a bdd package", in Proc. Design Automation Conf. (DAC), 1990, pp. 40-45.
46. N. Kazarinoff, Geometric inequalities. New York: Random House, 1961.
47. E. Kuh and D. Pederson, Principles of Circuit Synthesis. New York: McGraw-Hill, 1959.
48. F. Leyn, G. Gielen, and W. Sansen, "Analog small-signal modeling - part I: behavioral signal path modeling for analog integrated circuits", IEEE Trans, on Circuits and Systems II: analog and digital signal processing, vol. 48, no. 7, pp. 701-711, July 2001.
49. - "Analog small-signal modeling - part II: elementary transistor stages analyzed with behavioral signal path modeling", IEEE Trans, on Circuits and Systems II: analog and digital signal processing, vol. 48, no. 7, pp. 701-711, July 2001.
50. H. Liao and W. Dai, "Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels", in Proc. Int. Conf. on Computer Aided Design (ICCAD), 1995, pp. 704-711.
51. H. Liao, R. Wang, R. Chandra, and W. Dai, "S-parameter based macro model of distributed-lumped networks using Pade approximation", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 1993, pp. 2319-22.
52. J. Lillis, C. Cheng, S. Lin, and N. Chang, Interconnect analysis and synthesis. John Wiley, 1999.
53. P. M. Lin, Symbolic Network Analysis. Elsevier Science Publishers B. V., 1991.
54. - "'Sensitivity analysis of large linear networks using symbolic program", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 1992, pp. 1145-1148.
55. J. W. Liu, "Modification of the minimum degree algorithm by multiple elimination", ACM Trans. Math. Software, vol. 11, pp. 141-153, 1985.
56. A. Manthe, L. Zhao, and C.-J. R. Shi, "Symbolic analysis of analog circuits with hard nonlinearity", in Proc. Design Automation Conf. (DAC), 2003, pp. 542-545.
57. A. Manthe, L. Zhao, C.-J. R. Shi, and K. Mayaram, "Symbolic analysis of nonlinear analog circuits", in Proc. European Design and Test Conf. (DATE), 2003, pp. 1108-1109.
58. S. J. Mason, "Feedback theory - some properties of signal fbw graphs", Proc. IRE, vol. 45, pp. 829-838, 1953.
59. - "Feedback theory-further properties of signal fbw graphs", Proceedings of IRE, vol. 44, pp. 920-926, July 1956.
60. W. Mayeda and S. Seshu, "Topological formulas for networks", in Engineering Experimentation Station Bulletin 446, 1957, university of Illinois, Urbana.
61. S. Minato, "Zero-suppressed bdds for set manipulation in combinatorial problems", in Proc. Design Automation Conf. (DAC), 1993, pp. 272-277.
62. - Binary Decision Diagrams and Application for VLSI CAD. Boston: Kluwer Academic Publishers, 1996.
63. L. W. Nagel, "SPICE2: A computer program to simulate semiconductor circuits", Ph. D. dissertation, University of California, Berkeley, Berkeley CA, May 1975.
64. A. Odabasioglu, M. Celik, and L. Pileggi, "PRIMA: Passive reduced-order interconnect macromodeling algorithm", IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, pp. 645-654, 1998.
65. A. Pacelli, "A local circuit topology for inductive parasitics", in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2002, pp. 208-214.
66. L. T. Pillage and R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis", IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, pp. 352-366, April 1990.
67. L. T. Pillage, R. A. Rohrer, and C. Visweswariah, Electronic Circuit and System Simulation Methods. New York: McGraw-Hill, 1994.
68. Z. Qin and C.-K. Cheng, "RCLK-VJ network reduction with hurwitz polynomial approximation", in Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Jan. 2003, pp. 283-291.
69. Z. Qin and C. Cheng, "Realizable parasitic reduction using generalized Y - A transformation", in Proc. Design Automation Conf. (DAC), 2003, pp. 220-225.
70. T. Sasao and M. Fujita, Representations of Discrete Functions. Kluwer Academic Publishers, 1996.
71. M. Schetzen, The Volterra and Wiener Theory of Nonlinear Systems. New York: Wiley, 1981.
72. S. J. Seda, M. G. R. Degrauwe, and W. Fichtner, "A symbolic analysis tool for analog circuit design automation", in Proc. Int. Conf. on Computer Aided Design (ICCAD), Nov. 1988, pp. 488-491.
73. - "Lazy-expansion symbolic expression approximation in synap", in Proc. Int. Conf. on Computer Aided Design (ICCAD), Nov. 1992, pp. 310-317.
74. B. N. Sheehan, TICER: Realizable reduction of extracted RC circuits", in Proc. Int. Conf. on Computer Aided Design (ICCAD), 1999, pp. 200-203.
75. -, "Branch merge reduction of RLCM networks", in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2003, pp. 658-664.
76. C.-J. Shi and X.-D. Tan, "Symbolic analysis of large analog circuits with determinant decision diagrams", in Proc. Int. Conf. on Computer Aided Design (ICCAD), Nov. 1997, pp. 366-373.
77. - "Canonical symbolic analysis of large analog circuits with determinant decision diagrams", IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 1, pp. 1-18, Jan. 2000.
78. - "Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design", IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 7, pp. 813-827, April 2001.
79. M. Silveira, M. K. andl. Elfadel, and J. White, "A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits", in Proc. Int. Conf. on Computer Aided Design (ICCAD), 1996, pp. 288-294.
80. M. Silveira, M. Kamon, and J. White, "Efficient reduced-order modeling of frequencydependent coupling inductances associated with 3-D interconnect structures", in Proc. Design Automation Conf. (DAC), June 1995, pp. 376-380.
81. J. A. Starzky and A. Konczykowska, "Flowgraph analysis of large electronic networks", IEEE Trans, on Circuits and Systems, vol. 33, no. 3, pp. 302-315, March 1986.
82. S. X.-D. Tan, "A general s-domain hierarchical network reduction algorithm", in Proc. Int. Conf. on Computer Aided Design (ICCAD), 2003, pp. 650-657.
83. - "A general hierarchical circuit modeling and simulation algorithm", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2005, (in press).
84. S. X.-D. Tan, Z. Qi, and H. Li, "Hierarchical modeling and simulation of large analog circuits", in Proc. European Design and Test Conf. (DATE), Feb. 2004, pp. 740-741.
85. S. X.-D. Tan and C.-J. Shi, "Efficient DDD-based interpretable symbolic characterization of large analog circuits", IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E86-A, no. 12, pp. 3112-3118, Dec. 2003.
86. - "Efficient approximation of symbolic expressions for analog behavioral modeling and analysis", IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 6, pp. 907-918, June 2004.
87. S. X.-D. Tan and J. Yang, "Hurwitz stable model reduction for non-tree structured RLCK circuits", in IEEE Int. System-on-Chip Conf. (SOC), 2003, pp. 239-242.
88. S. X.-D. Tan and C.-J. Shi, "Parametric analog behavioral modeling based on cancellation-free ddds", in Proc. IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), Oct. 2002.
89. X. Tan and C.-J. Shi, "Hierarchical symbolic analysis of large analog circuits with determinant decision diagrams", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), vol. VI, 1998, pp. 318-321.
90. X.-D. Tan and C.-J. Shi, "Interpretable symbolic small-signal characterization of large analog circuits using determinant decision diagrams", in Proc. European Design and Test Conf. (DATE), 1999, pp. 448-453.
91. - "Hierarchical symbolic analysis of large analog circuits via determinant decision diagrams", IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 4, pp. 401-412, April 2000.
92. P. Vanassche, G. Gielen, and W. Sansen, "Symbolic modeling of periodically timevarying systems using harmonic transfer functions", IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 9, pp. 1011-1024, Sept. 2002.
93. W. Verhaegen and G. Gielen, "Efficient ddd-based symbolic analysis of large linear analog circuits", in Proc. Design Automation Conf. (DAC), June 2001, pp. 139-144.
94. - "Symbolic distortion analysis of analog integrated circuits", in Proc. European Conference on Circuit Theory and Design, Aug. 2001, pp. 1.21-1.24.
95. - "Symbolic determinant decision diagrams and their use for symbolic modeling of linear analog integrated circuits", Kluwer International Journal on Analog Integrated Circuits and Signal Processing, vol. 31, no. 2, pp. 119-130, May 2002.
96. J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design. New York, NY: Van Nostrand Reinhold, 1995.
97. P. Wambacq, G. Gielen, and W. Sansen, "Symbolic simulation of harmonic distortion in analog integrated circuits with weak nonlinearities" , in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), May 1990, pp. 536-539.
98. - "A cancellation-free algorithm for the symbolic simulation of large analog circuits", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), May 1992, pp. 1157-1160.
99. - "A new reliable approximation method for expanded symbolic network functions", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 1996, pp. 584-587.
100. P. Wambacq and W. Sansen, Distortion Analysis of Analog Integrated Circuits. Kluwer Academic Publishers, 1998.
101. J. Yang and S. X.-D. Tan, "An efficient algorithm for transient and distortion analysis of mildly nonlinear analog circuits", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2004, (to appear).
102. X. Yang, C.-K. Cheng, W. Ku, and R. Carragher, "Hurwitz stable reduced order modeling for RLC interconnect trees", in Proc. Int. Conf. on Computer Aided Design (ICCAD), Nov. 2000, pp. 222-228.
103. M. Yannakakis, "Computing the minimum fiU-in is np-complete", S1AM Journal on discrete mathematics, pp. 77-79, 1981.
104. W. C. Yengst, Procedures of modern network synthesis. New York: Macmillan, 1964.
105. Z. You, E. Sánchez-Sinencio, and J. P. de Gyvez, "Analog system-level fault diagnosis based on a symbolic method in the frequency domain", IEEE Trans. Instrumentation and Measurement, vol. 44, no. 1, pp. 28-35, Feb. 1995.
106. H. Yu and L. He, "Vector potential equivalent circuit based on PEEC inversion " in Proc. Design Automation Conf. (DAC), 2003, pp. 781-723.
107. Q. Yu and C. Sechen, "A unifled approach to the approximate symbolic analysis of large analog integrated circuits", IEEE Trans, on Circuits and Systems I: Fundamental Theory and Applications, vol. 43, no. 8, pp. 656-669, Aug. 1996.
108. G. Zhong, C. Koh, and K. Roy, "On-chip interconnect modeling by wire duplication", IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 11, pp. 1521-1532, 2003.