On-chip interconnect modeling by wire duplication

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 11, 2003, Pages 1521-1532

  Zhong, Guoan ^a   Koh, Cheng Kok ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Circuit; Inductance; Interconnect; Modeling

Indexed keywords

APPROXIMATION THEORY; INDUCTANCE; MATHEMATICAL MODELS; MATRIX ALGEBRA;

ON CHIP INTERCONNECT MODELING; WIRE DUPLICATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0242551588     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.818303     Document Type: Article

References (10)

1. A. E. Ruehli, "Inductance calculation in a complex integrated circuit environment," IBM J. Res. Devel., pp. 470-481, Sept. 1972.
2. B. Krauter and T. L. Pileggi, "Generating sparse partial inductance matrices with guaranteed stability," in Proc. Int. Conf. Computer Aided Design, 1995, pp. 45-52.
3. Z. He, M. Celik, and L. T. Pileggi, "SPIE: Sparse partial inductance extraction," in Proc. Design Automation Conf., 1997, pp. 137-140.
4. A. Devgan, H. Ji, and W. Dai, "How to efficiently capture on-chip inductance effects: introducing a new circuit element K," in Proc. Int. Conf. Computer Aided Design, 2000, pp. 150-155.
5. H. Ji, A. Devgan, and W. Dai, "KSim: A stable and efficient RKC simulator for capturing on-chip inductance effect," in Proc. Asia South Pacific Design Automation Conf., 2001, pp. 379-384.
6. M. Beattie and L. Pileggi, "Efficient inductance extraction via windowing," in Proc. Design Automation Test Europe Conf., 2001, pp. 430-436.
7. ____, "Modeling magnetic coupling for on-chip interconnect," in Proc. Design Automation Conf., 2001, pp. 335-340.
8. T. H. Chen, C. Luk, H. Kim, and C. C.-P. Chen, "INDUCTWISE: Inductance-wise interconnect simulator and extractor," in Proc. Int. Conf. Computer Aided Design, 2002, pp. 215-220.
9. H. Ji, "private communication," unpublished, 2003.
10. H. Eves, Elementary Matrix Theory. Boston, MA: Allyn and Bacon, 1966.