Hurwitz stable model reduction for non-tree structured RLCK circuits [IC interconnect applications]

Proceedings - IEEE International SOC Conference, SOCC 2003

Volumn , Issue , 2003, Pages 239-242

  Tan, S X D ^a   Yang, Junjie ^a  

^a University of California Riverside   (United States)

Author keywords

Application specific integrated circuits; Circuit testing; Coupling circuits; Integrated circuit interconnections; Integrated circuit modeling; Linear circuits; Reduced order systems; RLC circuits; Transfer functions; Tree graphs

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CIRCUIT RESONANCE; GRAPHIC METHODS; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; TIME DOMAIN ANALYSIS; TRANSFER FUNCTIONS; TREES (MATHEMATICS);

CIRCUIT TESTING; INTEGRATED CIRCUIT INTERCONNECTIONS; INTEGRATED CIRCUIT MODELING; LINEAR CIRCUITS; REDUCED ORDER SYSTEMS; RLC CIRCUIT; TREE GRAPH;

COUPLED CIRCUITS;

EID: 4344690084     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOC.2003.1241501     Document Type: Conference Paper

References (16)

1. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Reading, Massachusetts: Addison-Wesley Publishing Company, 1990.
2. P. Feldmann and R. W. Freund, "Efficient linear circuit analysis by Pade approximation via the Lanczos process", IEEE Trans. Computer-Aided Design, vol. 14, no. 5, pp. 639-649, Feb. 1995.
3. -, "Reduced-order modeling of large linear subcircuits via block Lanczos algorithm", in Proc. IEEE/ACM Design Automation Conf.(DAC), pp. 376-380, June. 1995.
4. -, "Reduced-order modeling of large linear subcircuits by means of the SyPVL algorithm", in Proc. IEEE Int. Conf. Computer-Aided Design (ICCAD), pp. 280-287, Nov. 1996.
5. J. Cong, L. He, C.-K. Koh andP. Padden "Performance Optimization of VLSI Interconnect Layout",Integration, the VLSI Journal, vol. 21, nos. 1 & 2, Nov. pp. 1-94, 1996.
6. C. K. Cheng, J. Lillis, S. Lin and N. H. Chang, Interconnect Analysis and Synthesis, New York:John Wiley & Sons, Inc., 2000.
7. B. W. Char, et. al., Maple V: Language Reference Manual, Springer-Verlag, 1991.
8. Y. Ismail and E. G. Friedman "DTT: direct truncation of the transfer function - an alternative to moment matching for tree structured interconnect", IEEE Trans. Computer-Aided Design, vol. 21, no. 2, pp. 131-144, Feb. 2002.
9. A. Odabasioglu, M. Celik and L. T. Pilagge, "Prima: passive reduced-order interconnect macromodeling algorithm,"IEEE Trans. on Computer-Aided Design, vol. 17, no. 8, pp. 645-654, Aug. 1998.
10. L. T. Pillage and R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. Computer-Aided Design, vol. 9, pp. 352-366, Apr. 1990.
11. C.-J. Shi and X.-D. Tan, "Canonical symbolic analysis of large analog circuits with determinant decision diagrams",IEEE Trans. Computer-Aided Design, vol. 19, no. 1, pp. 1-18, Jan. 2000.
12. C.-J. Shi and X.-D. Tan, "Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design", IEEE Trans. Computer-Aided Design, vol. 20, No. 7, pp. 813-827, July 2001.
13. M. Silveira, M. Kamon, and J. White, "Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures", in Proc. IEEE/ACM Design Automation Conf.(DAC), pp. 376-380, June 1995.
14. M. Silveira, M. Kamon, I. Elfadel and J. White, "A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits", in Proc. IEEE Int. Conf. Computer-Aided Design (ICCAD), pp. 288-294, Nov. 1996.
15. C.T. Chen, "Linear System Theory and Design", Oxford Univ. Press, 3rd Ed., 1999.
16. X. Yang, C.-K. Cheng, W.H. Ku, R. J. Carragher "Hurwitz stable reduced order modeling for RLC interconnect trees", in Proc. IEEE Int. Conf. Computer-Aided Design (ICCAD), pp. 222-228, Nov. 2000.