Macromodeling for RF passives via circuit reduction of VPEC model

2004 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems: Digest of Papers

Volumn , Issue , 2004, Pages 199-202

  Yu, Hao ^a   He, Lei ^a   Tan, Sheldon X D ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b University of California Riverside   (United States)

Author keywords

Hierarchical Circuit Reduction; RF Passives Modeling; VPEC Model

Indexed keywords

HIERARCHICAL CIRCUIT REDUCTION; MACRO-MODELS; RF PASSIVES MODELING; VPEC MODELS;

COMPUTER SIMULATION; EQUIVALENT CIRCUITS; FUNCTIONS; MATHEMATICAL MODELS; MATRIX ALGEBRA; OPTIMIZATION; TIME DOMAIN ANALYSIS; VECTORS;

INTEGRATED CIRCUITS;

EID: 20344382958     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. D. Allstot, K. Choi, and J. Park, Parasitic-Aware Optimization of CMOS RF circuits. Kluwer Academic Publishers, 2003.
2. A. E. Ruehli, Equivalent circuits models for three dimensional multiconductor systems, IEEE Trans. on Microwave Theory and Techniques, pp. 216-220, 1974.
3. K. Narbos and J. White, FastCap: A multipole accelerated 3D capacitance extraction program, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 11, pp. 1447-1459, 1991.
4. M. Kamon, M. Tsuk, and J. White, FastHenry: a multipole-accelerated 3D inductance extraction program, IEEE Trans. on Microwave Theory and Techniques, pp. 1750-1758, Sept. 1994.
5. A. M. Niknejad and R. G. Meyer, Analysis of eddy current losses over conductive substrates with applications to monolithic inductors and transformers. IEEE Trans. on Microwave Theory and Techniques, pp. 166-76, Jan. 2001.
6. A. Pacelli, A local circuit topology for inductive parasitics, in Proc. Int. Conf. on Computer Aided Design (ICCAD), pp. 208-214, 2002.
7. H. Yu and L. He, Vector potential equivalent circuit based on PEEC inversion, in Proc. Design Automation Conf. (DAC), pp. 781-723, 2003.
8. S. X.-D. Tan, A general s-domain hierarchical network reduction algorithm, in Proc. Int. Conf. on Computer Aided Design (ICCAD), pp. 650-657, 2003.
9. G. C. Temes and J. Lapatra, Introduction to circuit synthesis and design. Mcgraw-Hilll Book Company, 1977.
10. Z. He, M. Celik, and L. Pillegi, SPIE: Sparse partial inductance extraction, in Proc. Design Automation Conf. (DAC), pp. 137-140, 1997.
11. M. Beattie and L. Pileggi, Efficient inductance extraction via windowing, in Proc. European Design and Test Conf. (DATE), pp. 430-436, 2001.
12. Z. Qin and C. Cheng, Realizable parasitic reduction using generalized Y - Δ transformation, in Proc. Design Automation Conf. (DAC), pp. 220-225, 2003.
13. B. N. Sheehan, Branch merge reduction of RLCM networks, in Proc. Int. Conf. on Computer Aided Design (ICCAD), pp. 658-664, 2003.
14. C. S. Amin, M. H. Chowdhury, and Y. I. Ismail, Realizable rlck circuit crunching, in Proc. Design Automation Conf. (DAC), pp. 226-231, 2003.
15. S. X.-D. Tan, Z. Qi, and H. Li, Hierarchical modeling and simulation of large analog circuits, in Proc. European Design and Test Conf. (DATE), 2004.
16. B. Gustavsen and A. Semlyen, Enforcing passivity for admittance matrices approximated by rational functions. IEEE Transactions on Power Systems, vol. 16, pp. 97-104, 2001.
17. O. Brune, Synthesis of a finite two-terminal network whose driving point impedance is a prescribed function of frequency. Journal of Math. and Phys., vol. 10, pp. 191-236, 1931.
18. B. Razavi, RF Microelectronics. Prentice Hall, 1998.