Including higher-order moments of RC interconnections in layout-to-circuit extraction

Proceedings of European Design and Test Conference

Volumn , Issue , 1996, Pages 362-366

  Elias, P J H ^a   van der Meijs, N P ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK ANALYSIS; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS;

ELMORE DELAY PRESERVING REDUCTION; LAYOUT TO CIRCUIT EXTRACTION; MOMENTS PRESERVING REDUCTION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029735239     PISSN: 10661409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)