Hierarchical modeling and simulation of large analog circuits

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 740-741

  Tan, Sheldon X D ^a   Qi, Zhenyu ^a   Li, Hang ^a  

^a University of California Riverside   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONSTANT-ADMITTANCE STRATEGY; LARGE ANALOG CIRCUITS; RATIONAL FUNCTIONS; SUBCIRCUIT REDUCTION; CIRCUIT COMPLEXITY; CIRCUIT MODELING; FREQUENCY AND TIME DOMAINS; HIERARCHICAL MODEL; INTERCONNECT CIRCUITS; LINEAR ANALOG CIRCUITS; MODEL AND SIMULATION; SYMBOLIC ANALYSIS;

ALGORITHMS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; HIERARCHICAL SYSTEMS; MATHEMATICAL MODELS; POLYNOMIAL APPROXIMATION; THEOREM PROVING; VECTORS; EXHIBITIONS;

NETWORKS (CIRCUITS); ANALOG CIRCUITS;

EID: 3042611748     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268956     Document Type: Conference Paper

References (3)

1. Z. Qin and C-K. Cheng, "RCLK-VJ network reduction with Hurwitz polynomial approximation," Proc. Asia South Pacific Design Automation Conference (ASP-DAC), pp.283-291, Jan. 2003.
2. X.-D. S. Tan and C.-J. Richard Shi, "Parametric analog behavioral modeling based on cancellation-free DDDs. IEEE International Workshop on Behavioral Modeling and Simulation, Santa Rosa, CA, Oct., 2002.
3. S. X.-D. Tan, "A general s-domain hierarchical network reduction algorithm", Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2003.