INDUCTWISE: Inductance-wise interconnect simulator and extractor

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 215-220

  Chen, Tsung Hao ^a   Luk, Clement ^a   Kim, Hyungsuk ^a   Chen, Charlie Chung Ping ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHOLESKY DECOMPOSITION; INDUCTANCE EXTRACTION; PARTIAL ELEMENT EQUIVALENT CIRCUIT METHOD;

ALGORITHMS; CAPACITANCE; COMPUTER SIMULATION; EQUIVALENT CIRCUITS; INDUCTANCE; INVERSE PROBLEMS; MATHEMATICAL MODELS; MATRIX ALGEBRA; VLSI CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036911569     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774604     Document Type: Conference Paper

References (16)

1. H. Ji, A. Devgan, and W. Dai. Ksim: A stable and efficient rkc simulator for capturing on-chip inductance effect. In ASPDAC, June 2001.
2. M.W. Beattie and L.T. Pileggi. Inductance 101: Modeling and extraction. In DAC, June 2001.
3. K. Gala, D. Blaauw, J. Wang, V. Zolotov, and M. Zhao. Inductance 101: Analysis and design issues. In DAC, June 2001.
4. A.E. Ruehli. Inductance calculatioin in a complex integrated curcuit environment. IBM Journal of Research and Development, pages 470-481, September 1972.
5. M. Kamon, M.J. Tsuk, and J.K. White. Fasthenry: A multipole-accelerated 3-d inductance extraction program. In DAC, June 1993.
6. N. Chang, S. Lin, J. Lillis, and C.K. Cheng. Inteconnect Analysis and Synthesis. John Wiley & Sons Inc., 2000.
7. Z. He, M. Celik, and L.T. Pileggi. Spie: Sparse partial inductance extraction. In DAC, 1997.
8. B. Krauter and L.T. Pileggi. Generating sparse partial inductance matrices with guaranteed stability. In ICCAD, November 1995.
9. K.L. Shepard and Z. Tian. Return-limited inductances: A practical approach to on-chip inductance extraction. IEEE Trans. on Computer Aided Design of Integrated Ciurcuits and Systems, 19(4):425-436, April 2000.
10. K. Gala, V. Zolotov, R. Panda, B. Young, J. Wang, and D. Blaauw. On-chip inductance modeling and analysis. In DAC, June 2000.
11. M.W. Beattie and L.T. Pileggi. Modeling magnetic coupling for on-chip interconnect. In DAC, June 2001.
12. A. Devgan, H. Ji, and W. Dai. How to efficiently capture on-chip inductance effects: Introducing a new circuit element k. In ICCAD, November 2000.
13. http://whatis.techtarget.com/definition/0,,sid9_gci531197,00.html.
14. H. Zheng, B. Krauter, M. Beattie, and L. Pileggi. Window-based susceptance models for large-scale rlc circuit analysis. In DATE, 2002.
15. T.H. Chen and C.C.P. Chen. Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods. In DAC, June 2001.
16. L.W. Nagel. Spice2: A computer program to simulate semiconductor circuits. U.C. Berkely, ERL Memo ERL-M520, 1975.