Wideband passive multiport model order reduction and realization of RLCM circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 8, 2006, Pages 1496-1509

  Qi, Zhenyu ^a,b   Yu, Hao ^a,c   Liu, Pu ^a,b   Tan, Sheldon X D ^a,b   He, Lei ^a,c  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Behavioral modeling; Circuit simulation; Determinant decision diagrams; Model order reduction; Realization

Indexed keywords

BEHAVIORAL MODELING; CIRCUIT SIMULATION; DETERMINANT DECISION DIAGRAMS; INDUCTANCE CIRCUITS; MODEL ORDER REDUCTION; REALIZATION;

ALGORITHMS; CAPACITORS; COMPUTER SIMULATION; ELECTRIC INDUCTORS; EQUIVALENT CIRCUITS; FREQUENCY DOMAIN ANALYSIS; HIERARCHICAL SYSTEMS; RESISTORS;

INTEGRATED CIRCUITS;

EID: 33746626527     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.855937     Document Type: Article

References (45)

1. R. Achar, P. K. Gunupudi, M. Nakhla, and E. Chiprout, "Passive interconnect reduction algorithm for distributed/measured networks," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 4, pp. 287-301, Apr. 2000.
2. D. Allstot, K. Choi, and J. Park, Parasitic-Aware Optimization of CMOS RF Circuits. Boston, MA: Kluwer, 2003.
3. C. S. Amin, M. H. Chowdhury, and Y. I. Ismail, "Realizable RLCK circuit crunching," in Proc. DAC, Anaheim, CA, 2003, pp. 226-231.
4. B. D. O. Anderson and S. Vongpanitlerd, Network Analysis and Synthesis, Englewood Cliffs, NJ: Prentice-Hall, 1973.
5. M. Beattie and L. Pileggi, "Efficient inductance extraction via windowing," in Proc. Eur. DATE, Munich, Germany, 2001, pp. 430-436.
6. O. Brune, "Synthesis of a finite two-terminal network whose driving point impedance is a prescribed function of frequency," J. Math. Phys., vol. 10, no. 3, pp. 191-236, 1931.
7. J. P. C. P. Coelho and L. M. Silveira, "A convex programming approach for generating guaranteed passive approximations to tabulated frequency-data," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 23, no. 2, pp. 293-301, Feb. 2004.
8. E. Chiprout and M. S. Nakhla, "Analysis of interconnect networks using complex frequency hopping," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 14, no. 2, pp. 186-200, Feb. 1995.
9. C. P. Coelho, J. R. Phillips, and L. M. Silveira, "A convex programming approach to positive real rational approximation," in Proc. ICCAD, San Jose, CA, Nov. 2001, pp. 245-251.
10. P. J. H. Elias and N. P. van der Meijs, "Including higher-order moments of RC interconnections in layout-to-circuit extraction," in Proc. Eur. DATE, Paris, France, Mar. 1996, pp. 362-366.
11. P. Feldmann and R. W. Freund, "Efficient linear circuit analysis by Padé approximation via the Lanczos process," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 14, no. 5, pp. 639-649, May 1995.
12. R. W. Freund, "SPRIM: Structure-preserving reduced-order interconnect macromodeling," in Proc. ICCAD, San Jose, CA, 2004, pp. 80-87.
13. S. Grivet-Tklocia, I. A. Maio, and F. Canavero, "Recent advances in reduced-order modeling of complex interconnects," in Proc. Dig. Electrical Performance Electronic Packaging, Cambridge, MA, Oct. 2001, vol. 10, pp. 243-246.
14. B. Gustavsen and A. Semlyen, "Rational approximation of frequency domain responses by vector fitting," IEEE Trans. Power Del., vol. 14, no. 3, pp. 1052-1061, Mar. 1999.
15. X. Huang, V. Rahjavan, and R. A. Rohrer, "Awesim: A program for efficient analysis of linear(ized) circuits," in Proc. ICCAD, Santa Clara, CA, 1990, pp. 534-537.
16. Y. Ismail and E. G. Friedman, "DTT: Direct truncation of the transfer function - An alternative to moment matching for tree structured interconnect," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 21, no. 2, pp. 131-144, Feb. 2003.
17. M. Kamon, M. Tsuk, and J. White, "FastHenry: A multipole-accelerated 3-D inductance extraction program," IEEE Trans. Microw. Theory Tech., vol. 42, no. 9, pp. 1750-1758, Sep. 1994.
18. 3: A fast integral equation solver for efficient 3-dimensional extraction," in Proc. ICCAD, San Jose, CA, 1997, pp. 448-455.
19. C. Kashyap and B. Krauter, "A realizable driving point model for on-chip interconnect with inductance," in Proc. DAC, Los Angeles, CA, 2000, pp. 190-195.
20. K. J. Kerns and A. T. Yang, "Stable and efficient reduction of large, multiport RC network by pole analysis via congruence transformations, " IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 16, no. 7, pp. 734-744, Jul. 1998.
21. Y. Kim and D. Sylvester, Indigo: PEEC based RLC extraction and analysis tool for High-Speed On-Chip Interconnect, http://www.eecs.umich.edu/~kimyz/peec. htm, EECS Dept. Univ. Michigan.
22. J. Lillis, C. Cheng, S. Lin, and N. Chang, Interconnect Analysis and Synthesis. New York: Wiley, 1999.
23. Y. Massoud and J. White, "Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit crosstalk," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 3, pp. 286-291, Jun. 2002.
24. J. Morsey and A. C. Cangellaris, "PRIME: Passive realization of interconnect models from measured data," in Proc. Electrical Performance Electronic Packaging, Cambridge, MA, Oct. 2001, pp. 47-50.
25. K. Narbos and J. White, "FastCap: A multipole accelerated 3D capacitance extraction program," IEEE Trans. Comput.-Aided Des. Integr, Circuits Syst., vol. 10, no. 11, pp. 1447-1459, Nov. 1991.
26. A. Odabasioglu, M. Celik, and L. Pileggi, "PRIMA: Passive reduced-order interconnect macromodeling algorithm," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 17, no. 8, pp. 645-654, Aug. 1998.
27. A. Pacelli, "A local circuit topology for inductive parasitics," in Proc. ICCAD, San Jose, CA, 2002, pp. 208-214.
28. L. T. Pillage and R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 9, no. 4, pp. 352-366, Apr. 1990.
29. L. T. Pillage, R. A. Rohrer, and C. Visweswariah, Electronic Circuit and System Simulation Methods. New York: McGraw-Hill, 1994.
30. Z. Qi, S. X.-D. Tan, H. Yu, L. He, and P. Liu, "Wideband modeling of RF/analog circuits via hierarchical multi-point model order reduction," in Proc. ASPDAC, Shanghai, China, Jan. 2005, pp. 224-229.
31. Z. Qin and C. Cheng, "Realizable parasitic reduction using generalized y-Δ transformation," in Proc. DAC, Anaheim, CA, 2003, pp. 220-225.
32. B. Razavi, RF Microelectronics. Upper Saddle River, NJ: Prentice-Hall, 1998.
33. D. Saraswat, R. Achar, and M. Nakhla, "A fast algorithm and practical considerations for passive macromodeling of measured/simulated data," IEEE Trans. Adv. Packag., vol. 27, no. 1, pp. 57-70, Feb. 2004.
34. B. N. Sheehan, "TICER: Realizable reduction of extracted RC circuits," in Proc. ICCAD, San Jose, CA, 1999, pp. 200-203.
35. _, "Branch merge reduction of RLCM networks," in Proc. ICCAD, San Jose, CA, 2003, pp. 658-664.
36. C.-J. Shi and X.-D. Tan, "Canonical symbolic analysis of large analog circuits with determinant decision diagrams," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 19, no. 1, pp. 1-18, Jan. 2000.
37. M. Silveira, M. Kamon, I. Elfadel, and J. White, "A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits," in Proc. ICCAD, San Jose, CA, 1996, pp. 288-294.
38. J. Sturm, "Using SeDuMi 1.02, a Matlab Toolbox for optimization over symmetric cones," Optim. Methods. Softw., vol. 11-12, pp. 625-653, 1999.
39. S. X.-D. Tan, "A general s-domain hierarchical network reduction algorithm," in Proc. ICCAD, San Jose, CA, 2003, pp. 650-657.
40. S. X.-D. Tan, W. Guo, and Z. Qi, "Hierarchical approach to exact symbolic analysis of large analog circuits," in Proc. DAC, San Diego, CA, Jun. 2004, pp. 860-863.
41. S. X.-D. Tan, Z. Qi, and H. Li, "Hierarchical modeling and simulation of large analog circuits," in Proc. Eur. DATE, Paris, France, Feb. 2004, pp. 740-741.
42. X.-D. Tan and C.-J. Shi, "Hierarchical symbolic analysis of large analog circuits via determinant decision diagrams," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 19, no. 4, pp. 401-412, Apr. 2000.
43. G. C. Temes and J. Lapatra, Introduction to Circuit Synthesis and Design. New York: McGraw-Hill, 1977.
44. H. Yu and L. He, "Vector potential equivalent circuit based on PEEC inversion," in Proc. DAC, Anaheim, CA, 2003, pp. 723-781.
45. H. Yu, L. He, Z. Qi, and S. X.-D. Tan, "A wideband realizable circuit-reduction for RLCM interconnects," in Proc. ASPDAC, Shanghai, China, Jan. 2005, pp. 111-114.