Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 88-92

  Feldmann, Peter ^a   Liu, Frank ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATIONS; CLOCK DISTRIBUTION NETWORKS; LINEAR SUBCIRCUITS; MODEL ORDER REDUCTION (MOR);

ALGORITHMS; COMPUTER SIMULATION; CORRELATION METHODS; ELECTRIC POWER SYSTEMS; MATRIX ALGEBRA; TRANSFER FUNCTIONS;

VLSI CIRCUITS;

EID: 16244418081     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. K. J. Kerns and A. T. Yang, "Preservation of passivity during RLC network reduction via split congruence transformations," in Design Automation Conference, 1997, pp. 34-39.
3. K. Gallivan, E. Grimme, and P. Van Dooren, "A rational Lanczos algorithm for model reduction," Numerical Algorithms, vol. 12, no. 1-2, pp. 33-63, 1996.
4. R. W. Freund and P. Feldmann, "The SyMPVL algorithm and its applications to interconnect simulation," in Proceedings of the 1997 International Conference on Simulation of Semiconductor Processes and Devices. IEEE, 1997, pp. 113-116.
5. A. Odabasioglu, M. Celik, and L. Pileggi, "PRIMA: Passive reducedorder interconnect macromodeling algorithm," IEEE trans. on CAD, vol. 17, no. 8, pp. 645-654, 1998.
6. P. Feldmann, "Model order reduction techniques for linear systems with large numbers of terminals," in Proceedings of the Design, Automation and Test in Europe Conference 2004. IEEE Computer Society Press, 2003.
7. S. Kapur and D. E. Long, "IES3: a fast integral equation solver for efficient 3-dimensional extraction," in Proceedings of the 1997 International Conference on Computer-aided Design. IEEE, 1997, pp. 448-455.