-
1
-
-
0036916123
-
A local circuit topology for inductive parasitics
-
A. Pacelli, "A local circuit topology for inductive parasitics," in ICCAD, pp. 208-214, 2002.
-
(2002)
ICCAD
, pp. 208-214
-
-
Pacelli, A.1
-
2
-
-
0016035432
-
Equivalent circuits models for three dimensional multiconductor systems
-
A. E. Ruehli, "Equivalent circuits models for three dimensional multiconductor systems," IEEE Trans. on MIT, pp. 216-220, 1974.
-
(1974)
IEEE Trans. on MIT
, pp. 216-220
-
-
Ruehli, A.E.1
-
3
-
-
0030645057
-
SPIE: Sparse partial inductance extraction
-
Z. He, M. Celik, and L. Pillegi, "SPIE: Sparse partial inductance extraction," in 34th DAC, pp. 137-140, 1997.
-
(1997)
34th DAC
, pp. 137-140
-
-
He, Z.1
Celik, M.2
Pillegi, L.3
-
4
-
-
0001144063
-
Return-limited inductances: A practical approach to on-chip inductance extraction
-
K. Shepard and Z. Tian, "Return-limited inductances: A practical approach to on-chip inductance extraction," IEEE Trans. on CAD, vol. 19, no. 4, pp. 425-436, 2000.
-
(2000)
IEEE Trans. on CAD
, vol.19
, Issue.4
, pp. 425-436
-
-
Shepard, K.1
Tian, Z.2
-
5
-
-
0029521458
-
Generating sparse partial inductance matrices with guaranteed stability
-
B. Krauter and L. Pileggi, "Generating sparse partial inductance matrices with guaranteed stability," in ICCAD, pp. 45-52, 1995.
-
(1995)
ICCAD
, pp. 45-52
-
-
Krauter, B.1
Pileggi, L.2
-
6
-
-
0034474751
-
How to efficiently capture on-chip inductance effects: Introducing a new circuit element K
-
A. Devgan, H. Ji, and W. Dai, "How to efficiently capture on-chip inductance effects: introducing a new circuit element K," in ICCAD, pp. 150-155, 2000.
-
(2000)
ICCAD
, pp. 150-155
-
-
Devgan, A.1
Ji, H.2
Dai, W.3
-
7
-
-
84949799397
-
Ksim: A stable and efficient RKC simulator for capturing on-chip inductance effect
-
H. Ji, A. Devgan, and W. Dai, "Ksim: A stable and efficient RKC simulator for capturing on-chip inductance effect," in 38th DAC, pp. 379-384, 2001.
-
(2001)
38th DAC
, pp. 379-384
-
-
Ji, H.1
Devgan, A.2
Dai, W.3
-
8
-
-
0042694159
-
Efficient inductance extraction via windowing
-
M. Beattie and L. Pileggi, "Efficient inductance extraction via windowing," in DATE, pp. 430-436, 2001.
-
(2001)
DATE
, pp. 430-436
-
-
Beattie, M.1
Pileggi, L.2
-
9
-
-
0036911692
-
On-chip interconnect modeling by wire duplication
-
G. Zhong, C. Koh, and K. Roy, "On-chip interconnect modeling by wire duplication," in ICCAD, pp. 341-346, 2002.
-
(2002)
ICCAD
, pp. 341-346
-
-
Zhong, G.1
Koh, C.2
Roy, K.3
-
10
-
-
0028498583
-
FastHenry: A multipole-accelerated 3D inductance extraction program
-
M. Kamon, M. Tsuk, and J. White, "FastHenry: a multipole-accelerated 3D inductance extraction program," IEEE Trans. on MIT, 1994.
-
(1994)
IEEE Trans. on MIT
-
-
Kamon, M.1
Tsuk, M.2
White, J.3
-
11
-
-
0042694162
-
Vector potential equivalent circuit based on PEEC inversion
-
H. Yu and L. He, "Vector potential equivalent circuit based on PEEC inversion," in UCLA EE Technical Report, http://eda.ee.ucla.edu/publications.html, 2003.
-
(2003)
UCLA EE Technical Report
-
-
Yu, H.1
He, L.2
-
12
-
-
0026255002
-
FastCap: A multipole accelerated 3D capacitance extraction program
-
K. Narbos and J. White, "FastCap: A multipole accelerated 3D capacitance extraction program," IEEE Trans. on CAD, vol. 10, no. 11, pp. 1447-1459, 1991.
-
(1991)
IEEE Trans. on CAD
, vol.10
, Issue.11
, pp. 1447-1459
-
-
Narbos, K.1
White, J.2
-
13
-
-
0003851263
-
Inductance calculations: Working formulas and tables
-
New York
-
F. Grover, "Inductance calculations: Working formulas and tables," in Dover Publications, New York, 1946.
-
(1946)
Dover Publications
-
-
Grover, F.1
-
14
-
-
0033712809
-
On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation
-
X. Qi, G. Wang, Z. Yu, R. Dutton, T. Young, and N. Chang, "On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation," in CICC, pp. 487-490, 2000.
-
(2000)
CICC
, pp. 487-490
-
-
Qi, X.1
Wang, G.2
Yu, Z.3
Dutton, R.4
Young, T.5
Chang, N.6
-
15
-
-
0036045544
-
On the efficacy of simplified 2D on-chip inductance models
-
T. Lin, M. W. Beattie, and L. T. Pileggi, "On the efficacy of simplified 2D on-chip inductance models," in 39th DAC, 2002.
-
(2002)
39th DAC
-
-
Lin, T.1
Beattie, M.W.2
Pileggi, L.T.3
|