메뉴 건너뛰기




Volumn 24, Issue 8, 2005, Pages 1283-1294

A provably passive and cost-efficient model for inductive interconnects

Author keywords

Circuit simulation; Inductance sparsification; Interconnect modeling

Indexed keywords

COMPUTER SIMULATION; COST EFFECTIVENESS; ELECTRIC NETWORK ANALYSIS; INDUCTANCE; MATHEMATICAL MODELS; MATRIX ALGEBRA;

EID: 23744433491     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.850820     Document Type: Article
Times cited : (8)

References (26)
  • 3
    • 0016035432 scopus 로고
    • Equivalent circuits models for three dimensional multi-conductor systems
    • A. E. Ruehli, "Equivalent circuits models for three dimensional multi-conductor systems," IEEE Trans. Microw. Theory Tech., vol. MTT-22, no. 3, pp. 216-220, 1974.
    • (1974) IEEE Trans. Microw. Theory Tech. , vol.MTT-22 , Issue.3 , pp. 216-220
    • Ruehli, A.E.1
  • 4
    • 0026255002 scopus 로고
    • FastCap: A multipole accelerated 3D capacitance extraction program
    • Nov.
    • K. Narbos and J. White, "FastCap: A multipole accelerated 3D capacitance extraction program," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 10, no. 11, pp. 1447-1459, Nov. 1991.
    • (1991) IEEE Trans. Comput.-aided Des. Integr. Circuits Syst. , vol.10 , Issue.11 , pp. 1447-1459
    • Narbos, K.1    White, J.2
  • 5
    • 0028498583 scopus 로고
    • FastHenry: A multipole-accelerated 3D inductance extraction program
    • Sep.
    • M. Kamon, M. Tsuk, and J. White, "FastHenry: A multipole-accelerated 3D inductance extraction program," IEEE Trans. Microw. Theory Tech., vol. 42, no. 9, pp. 1750-1758, Sep. 1994.
    • (1994) IEEE Trans. Microw. Theory Tech. , vol.42 , Issue.9 , pp. 1750-1758
    • Kamon, M.1    Tsuk, M.2    White, J.3
  • 6
    • 0034823548 scopus 로고    scopus 로고
    • Analysis of eddy current losses over conductive substrates with applications to monolithic inductors and transformers
    • Jan.
    • A. M. Niknejad and R. G. Meyer, "Analysis of eddy current losses over conductive substrates with applications to monolithic inductors and transformers," IEEE Trans. Microw. Theory Tech., vol. 49, no. 1, pp. 166-176, Jan. 2001.
    • (2001) IEEE Trans. Microw. Theory Tech. , vol.49 , Issue.1 , pp. 166-176
    • Niknejad, A.M.1    Meyer, R.G.2
  • 8
    • 0001144063 scopus 로고    scopus 로고
    • Return-limited inductances: A practical approach to on-chip inductance extraction
    • Apr.
    • K. Shepard and Z. Tian, "Return-limited inductances: A practical approach to on-chip inductance extraction," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 19, no. 4, pp. 425-436, Apr. 2000.
    • (2000) IEEE Trans. Comput.-aided Des. Integr. Circuits Syst. , vol.19 , Issue.4 , pp. 425-436
    • Shepard, K.1    Tian, Z.2
  • 9
    • 0029521458 scopus 로고
    • Generating sparse partial inductance matrices with guaranteed stability
    • San Jose, CA
    • B. Krauter and L. Pileggi, "Generating sparse partial inductance matrices with guaranteed stability," in Proc. Int. Conf. Computer-Aided Design (ICCAD), San Jose, CA, 1995, pp. 45-52.
    • (1995) Proc. Int. Conf. Computer-aided Design (ICCAD) , pp. 45-52
    • Krauter, B.1    Pileggi, L.2
  • 10
    • 0034474751 scopus 로고    scopus 로고
    • How to efficiently capture on-chip inductance effects: Introducing a new circuit element K
    • Santa Clara, CA
    • A. Devgan, H. Ji, and W. Dai, "How to efficiently capture on-chip inductance effects: Introducing a new circuit element K," in Proc. Int. Conf. Computer-Aided Design (ICCAD), Santa Clara, CA, 2000, pp. 150-155.
    • (2000) Proc. Int. Conf. Computer-aided Design (ICCAD) , pp. 150-155
    • Devgan, A.1    Ji, H.2    Dai, W.3
  • 12
    • 84949799397 scopus 로고    scopus 로고
    • Ksim: A stable and efficient RKC simulator for capturing on-chip inductance effect
    • Yokohama, Japan
    • H. Ji, A. Devgan, and W. Dai, "Ksim: A stable and efficient RKC simulator for capturing on-chip inductance effect," in Proc. Asia South Pacific Design Automation Conf. (ASPDAC), Yokohama, Japan, 2001, pp. 379-384.
    • (2001) Proc. Asia South Pacific Design Automation Conf. (ASPDAC) , pp. 379-384
    • Ji, H.1    Devgan, A.2    Dai, W.3
  • 13
    • 0038444634 scopus 로고    scopus 로고
    • Inductwise: Inductance-wise interconnect simulator and extractor
    • Jul.
    • T. Chen, C. Luk, and C. Chen, "Inductwise: Inductance-wise interconnect simulator and extractor," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 22, no. 7, pp. 884-894, Jul. 2003.
    • (2003) IEEE Trans. Comput.-aided Des. Integr. Circuits Syst. , vol.22 , Issue.7 , pp. 884-894
    • Chen, T.1    Luk, C.2    Chen, C.3
  • 15
    • 0036916123 scopus 로고    scopus 로고
    • A local circuit topology for inductive parasitics
    • San Jose, CA
    • A. Pacelli, "A local circuit topology for inductive parasitics," in Proc. Int. Conf. Computer-Aided Design (ICCAD), San Jose, CA, 2002, pp. 208-214.
    • (2002) Proc. Int. Conf. Computer-aided Design (ICCAD) , pp. 208-214
    • Pacelli, A.1
  • 16
    • 84861433573 scopus 로고    scopus 로고
    • A wideband hierarchical circuit reduction for massively coupled interconnects
    • Shanghai, China
    • H. Yu, L. He, Z. Qi, and S. Tan, "A wideband hierarchical circuit reduction for massively coupled interconnects," presented at the Asia South Pacific Design Automation Conf. (ASPDAC), Shanghai, China, 2005.
    • (2005) Asia South Pacific Design Automation Conf. (ASPDAC)
    • Yu, H.1    He, L.2    Qi, Z.3    Tan, S.4
  • 17
    • 0347409183 scopus 로고    scopus 로고
    • A general s-domain hierarchical network reduction algorithm
    • San Jose, CA
    • S. X.-D. Tan, "A general s-domain hierarchical network reduction algorithm," in Proc. Int. Conf. Computer-Aided Design (ICCAD), San Jose, CA, 2003, pp. 650-657.
    • (2003) Proc. Int. Conf. Computer-aided Design (ICCAD) , pp. 650-657
    • Tan, S.X.-D.1
  • 18
    • 0030686706 scopus 로고    scopus 로고
    • Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology
    • Anaheim, CA
    • J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali, and S. H.-C. Yen, "Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology," in Proc. Design Automation Conf. (DAC), Anaheim, CA, 1997, pp. 627-632.
    • (1997) Proc. Design Automation Conf. (DAC) , pp. 627-632
    • Cong, J.1    He, L.2    Kahng, A.B.3    Noice, D.4    Shirali, N.5    Yen, S.H.-C.6
  • 21
    • 0011709278 scopus 로고
    • Englewood Cliffs, NJ: Prentice-Hall
    • V. Valkenburg, Linear Circuits. Englewood Cliffs, NJ: Prentice-Hall, 1982.
    • (1982) Linear Circuits
    • Valkenburg, V.1
  • 24
    • 0034840755 scopus 로고    scopus 로고
    • Using conduction modes basis functions for efficient electromagnetic analysis of on-chip and off-chip interconnect
    • Las Vegas, NV
    • D. Luca, A. Sangiovanni-Vincetelli, and J. White, "Using conduction modes basis functions for efficient electromagnetic analysis of on-chip and off-chip interconnect," in Proc. Design Automation Conf. (DAC), Las Vegas, NV, 2001, pp. 563-566.
    • (2001) Proc. Design Automation Conf. (DAC) , pp. 563-566
    • Luca, D.1    Sangiovanni-Vincetelli, A.2    White, J.3
  • 26
    • 0036625314 scopus 로고    scopus 로고
    • Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit crosstalk
    • Mar.
    • Y. Massoud and J. White, "Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit crosstalk," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 3, pp. 286-291, Mar. 2002.
    • (2002) IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol.10 , Issue.3 , pp. 286-291
    • Massoud, Y.1    White, J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.