An efficient method for terminal reduction of interconnect circuits considering delay variations

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 821-826

  Liu, Pu ^a   Tan, Sheldon X D ^a   Li, Hang ^a   Qi, Zhenyu ^a   Kong, Jun ^b   McGaughy, Bruce ^b   He, Lei ^c  

^a University of California ^*  (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; COMPUTER SIMULATION; DELAY CIRCUITS; FINITE ELEMENT METHOD; MATHEMATICAL MODELS; VLSI CIRCUITS;

INTERCONNECT CIRCUITS; SINGULAR VALUE DECOMPOSITION (SVD);

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 33751428898     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560176     Document Type: Conference Paper

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