Design of low-error fixed-width multipliers for DSP applications

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 46, Issue 6, 1999, Pages 836-842

  Jou, Jer Min ^a   Kuang, Shiann Rong ^a   Chen, Ren Der ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COST EFFECTIVENESS; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; ECHO SUPPRESSION; ELECTRIC NETWORK SYNTHESIS; MULTIMEDIA SYSTEMS; SIGNAL FILTERING AND PREDICTION; WAVELET TRANSFORMS;

CARRY GENERATING CIRCUITS; PARALLEL MULTIPLIERS;

MULTIPLYING CIRCUITS;

EID: 0033149483     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.769795     Document Type: Article

References (9)

1. C.S. Wallace, "A suggestion for a fast multiplier," IEEE Trans. Electron. Comput., vol. EC-13, pp. 14-17, 1964.
2. C.R. Baugh and B.A. Wooley, "A two's complement parallel array multiplication algorithm," IEEE Trans. Comput., vol. C-22, pp. 1045-1047, Dec. 1973.
3. L. Dadda, "On parallel digital multipliers," Aha Frequenz., vol. 45, pp. 574-580, 1976.
4. S.R. Kuang, J.M. Jou, and Y.L. Chen, "The design of an adaptive on-line binary arithmetic coding chip," IEEE Trans. Circuits Syst. I, vol. 45, pp. 693-706, July 1998.
5. T.J. Terrell, Introduction to Digital Filters. New York: Wiley, 1988.
6. S.S. Kidambi, F. El-Guibaly, and A. Antoniou, "Area-efficient multipliers for digital signal processing applications," IEEE Trans. Circuits Syst. II, vol. 43, pp. 90-94, 1996.
7. G. Strang and T. Nguyen, Wavelets and Filter Banks. Wellesley, MA: Wellesley-Cambridge, 1996.
8. 0.6 μm 1P3M technology manual, Chip Implementation Center, National Science Council, R.O.C., 1996.
9. S.-L. Kuang, "On the design of data compression and color correction ASIC's with some new high level synthesis approaches," Ph.D. dissertation, Dept. of Electron. Eng., National Cheng Kung Univ., Taiwan, R.O.C., June 1998.