A virtual clock enhancement method for DDS using an analog delay line

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 7, 2001, Pages 1158-1161

  Richter, Raik ^a,b   Jentschel, Hans Joachim ^a,b  

^a IEEE   (Germany)

^b DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG DELAY LINE; DELAY LOCKED LOOP; DIRECT DIGITAL SYNTHESIS; NOISE SHAPING; VIRTUAL CLOCK ENHANCEMENT;

DELAY CIRCUITS; DIGITAL INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; ELECTRONIC TIMING DEVICES; PHASE SHIFTERS; SIGNAL GENERATORS; SIGNAL NOISE MEASUREMENT; SPECTRUM ANALYSIS;

TIMING CIRCUITS;

EID: 0035392226     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.933477     Document Type: Article

References (5)

1. A 2-V, 2-GHz low-power direct digital frequency synthesizer chip-set for wireless communication
2. A low-power CMOS digitally synthesized 0-13 MHz agile sinewave generator
3. A DDS synthesizer with time domain interpolator
4. A fast frequency-switching synthesizer with an integration circuit