Reduced power dissipation through truncated multiplication

Proceedings - IEEE Alessandro Volta Memorial Workshop on Low-Power Design, VOLTA 1999

Volumn , Issue , 1999, Pages 61-69

  Schulte, Michael J ^a   Stine, James E ^a   Jansen, John G ^b  

^a Lehigh University   (United States)

^b NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL SIGNAL PROCESSING; ELECTRIC POWER SUPPLIES TO APPARATUS; PARALLEL PROCESSING SYSTEMS; SIGNAL PROCESSING;

DESIGN AND IMPLEMENTATIONS; DIGITAL SIGNAL PROCESSING SYSTEMS; PARALLEL MULTIPLIERS; ROUNDED PRODUCTS; TRUNCATED MULTIPLICATION; TRUNCATED MULTIPLIERS;

ELECTRIC LOSSES;

EID: 84894574742     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPD.1999.750404     Document Type: Conference Paper

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