-
2
-
-
84976692936
-
"Code generation for expressions with common subexpressions,"
-
vol. 24. no. 1, pp. 146-160, 1977.
-
A. V. Aho, S. C. Johnson, and J. D, Ullman, "Code generation for expressions with common subexpressions," J. ACM, vol. 24. no. 1, pp. 146-160, 1977.
-
J. ACM
-
-
Aho, A.V.1
Johnson, S.C.2
Ullman, J.D.3
-
3
-
-
33747754421
-
"A compound primitive operator approach to the realization of video sub-band filter banks,"
-
ICASSP93, pp. 1-405-4408.
-
D. R. Bull, G. Wacey, J. J. Stone, and J. M. Soloff, "A compound primitive operator approach to the realization of video sub-band filter banks," Pmc. Int. Conf. Accoust., Speech, Signal Processing, ICASSP93, pp. 1-405-4408.
-
Pmc. Int. Conf. Accoust., Speech, Signal Processing
-
-
Bull, D.R.1
Wacey, G.2
Stone, J.J.3
Soloff, J.M.4
-
4
-
-
0026172788
-
"Primitive operator digital filters," 1EE
-
vol. 138, no. 3. pp. 401-412, June 1991.
-
D. R. Bull and D. H. Horrocks, "Primitive operator digital filters," 1EE Pmc. G, vol. 138, no. 3. pp. 401-412, June 1991.
-
Pmc. G
-
-
Bull, D.R.1
Horrocks, D.H.2
-
5
-
-
0027237925
-
"Realization techniques for primitive operator infinite impulse response digital filters."
-
ISCAS-1993. pp. 607-610.
-
_, "Realization techniques for primitive operator infinite impulse response digital filters." Pmc. Int. Symp. Circuits Syst., ISCAS-1993. pp. 607-610.
-
Pmc. Int. Symp. Circuits Syst.
-
-
-
6
-
-
0027246925
-
"An architectural transformation program for uptimization of digital systems by multi-level decomposition,"
-
1993, pp. 343-348.
-
A. Chattcrjcc and R. K. Roy, "An architectural transformation program for uptimization of digital systems by multi-level decomposition," P roc. 30th ACM/IEEE Design Automation Conf., 1993, pp. 343-348.
-
P Roc. 30th ACM/IEEE Design Automation Conf.
-
-
Chattcrjcc, A.1
Roy, R.K.2
-
7
-
-
0027852146
-
"Greedy hardware optimization for linear digital circuits using number splitting and refac torization,"
-
vol. 1, pp. 423-431, Dec. 1993.
-
|7] A. Chatterjee, K. K. Roy, and M A. d'Abreu, "Greedy hardware optimization for linear digital circuits using number splitting and refac torization," IEEE Trans. VLSI Syst., vol. 1, pp. 423-431, Dec. 1993.
-
IEEE Trans. VLSI Syst.
-
-
Chatterjee, A.1
Roy, K.K.2
D'Abreu, M.A.3
-
8
-
-
0028526552
-
"Multiplier blocks arid the complexity of {HR} structures,"
-
vol. 30, no. 22, pp. 1841-1842, Oct 1994.
-
A. G. Dempster and M. D. Macleod, "Multiplier blocks arid the complexity of {HR} structures," Electron, leu., vol. 30, no. 22, pp. 1841-1842, Oct 1994.
-
Electron, Leu.
-
-
Dempster, A.G.1
Macleod, M.D.2
-
9
-
-
0028523075
-
"Constant integer multiplication using minimum adders,"
-
vol. 141. Oct. 1994, pp/ 407-4113.
-
_, "Constant integer multiplication using minimum adders," 1EE Pmc. Circuits Devices Syst, vol. 141. Oct. 1994, pp/ 407-4113.
-
1EE Pmc. Circuits Devices Syst
-
-
-
10
-
-
0026293034
-
" Optimization of canonic signed digit multipliers for filter design,"
-
Singapore, June 1991, pp. 1992-1995.
-
R. Hartley, " Optimization of canonic signed digit multipliers for filter design," Pmc. IEEE Int. Svrnp. Circuits Sysl., Singapore, June 1991, pp. 1992-1995.
-
Pmc. IEEE Int. Svrnp. Circuits Sysl.
-
-
Hartley, R.1
-
11
-
-
0028532666
-
"Optimizing pipelined networks of associative and commutative operators,"
-
vol. 13. pp. 1418-1425, Nov. 1994.
-
R. Hartley and A. E. Casavant. "Optimizing pipelined networks of associative and commutative operators," IEEE Tram. Computer-Aided Design, vol. 13. pp. 1418-1425, Nov. 1994.
-
IEEE Tram. Computer-Aided Design
-
-
Hartley, R.1
Casavant, A.E.2
-
12
-
-
0024055843
-
"Behavioral to structural translation in a bit-serial silicon compiler,"
-
vol. 7, pp. 877-886, Aug. 1988.
-
R. I. Hartley and J. R. Jasica. "Behavioral to structural translation in a bit-serial silicon compiler," IEEE Trans. Computer-Aided Design, vol. 7, pp. 877-886, Aug. 1988.
-
IEEE Trans. Computer-Aided Design
-
-
Hartley, R.I.1
Jasica, J.R.2
-
13
-
-
85033538540
-
"A silicon compiler for high-speed CMOS multirate FIR digital filters,"
-
San Diego, CA, May 1992, pp. 1348-1351.
-
R. Hawley, T. Lin, and H. Samueli, "A silicon compiler for high-speed CMOS multirate FIR digital filters," Pmc: IEEE Int. Symp. Circuits Syst., San Diego, CA, May 1992, pp. 1348-1351.
-
Pmc: IEEE Int. Symp. Circuits Syst.
-
-
Hawley, R.1
Lin, T.2
Samueli, H.3
-
14
-
-
0027211367
-
"Critical path minimization using retiming and algebraic speed-up,"
-
1993. pp. 573-577.
-
Z. Iqbal, M. Potkonjak, S. Dcy, and A. Parker, "Critical path minimization using retiming and algebraic speed-up," Pmc. 30th ACM/IEEE Design Automation Conf., 1993. pp. 573-577.
-
Pmc. 30th ACM/IEEE Design Automation Conf.
-
-
Iqbal, Z.1
Potkonjak, M.2
Dcy, S.3
Parker, A.4
-
15
-
-
0026185636
-
"FIRGEN: A computer-aided design system for high-performance {FIR} filter integrated circuits
-
vol. 39, pp. 1655-1668. July 1991.
-
R. Jain, P. T. Yang, and T. Yoshino, "FIRGEN: A computer-aided design system for high-performance {FIR} filter integrated circuits, IEEE Trans. Signal Processing, vol. 39, pp. 1655-1668. July 1991.
-
IEEE Trans. Signal Processing
-
-
Jain, R.1
Yang, P.T.2
Yoshino, T.3
-
17
-
-
0028590412
-
"Efficient substitution of multiple constant multiplications by shifts and additions using iterative pairwise matching,"
-
1994, pp. 189-194.
-
|17| M. Potkonjak, M. B. Srivastava, and A. Chandrakasan, "Efficient substitution of multiple constant multiplications by shifts and additions using iterative pairwise matching," DAC-94, Proc. 31st ACM/IEEE Design Automation Con}., 1994, pp. 189-194.
-
DAC-94, Proc. 31st ACM/IEEE Design Automation Con}.
-
-
Potkonjak, M.1
Srivastava, M.B.2
Chandrakasan, A.3
-
19
-
-
0026172137
-
"Fast prototyping of data path intensive architecture,"
-
vol. 8, no. 2, pp. 40 51. 1991.
-
J. Rabaey, C. Chu, P. Hoang. and M. Polkonjak. "Fast prototyping of data path intensive architecture," IEEE Design Test, vol. 8, no. 2, pp. 40 51. 1991.
-
IEEE Design Test
-
-
Rabaey, J.1
Chu, C.2
Hoang, P.3
Polkonjak, M.4
-
20
-
-
77957223221
-
"Binary arithmetic,"
-
New York: Academic. 1966, vol. 1, pp. 231-308.
-
R. W. Reitwiesner. "Binary arithmetic," Advances in Computers. New York: Academic. 1966, vol. 1, pp. 231-308.
-
Advances in Computers.
-
-
Reitwiesner, R.W.1
-
21
-
-
0027152990
-
"A design automation system for VLSI digital filters with invariant transfer function,"
-
ISCAS-1993, pp. 631-634.
-
G. Wacey and D. R, Bull. "A design automation system for VLSI digital filters with invariant transfer function," Proc. Int. Symp. Circuits Syst., ISCAS-1993, pp. 631-634.
-
Proc. Int. Symp. Circuits Syst.
-
-
Wacey, G.1
Bull, D.R.2
|