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33845577275
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A digital frequency synthesizer
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Mar.
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A 150-MHz direct digital frequency synthesizer in 1.25-μm CMOS with -90-dBc spurious performance
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Dec.
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Nicholas III, H.T.1
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A 200 MHz quadrature digital synthesizer/mixer in 0.8 μm CMOS
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Mar.
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Tan, L.K.1
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A 800 MHz quadrature digital synthesizer with ECL-compatible output drivers in 0.8 μm CMOS
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Dec.
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Tan, L.K.1
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0028076597
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A low-power CMOS digitally synthesized 0-13 MHz agile sinewave generator
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G. Chang, A. Rofougaran, M. Ku, A. A. Abidi, and H. Samueli, "A low-power CMOS digitally synthesized 0-13 MHz agile sinewave generator," in Proc. Int. Solid-State Circuits Conf., 1994, pp. 32-33.
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Chang, G.1
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A high-speed direct frequency synthesizer
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Feb.
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Saul, P.H.1
Taylor, D.G.2
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7
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0024027811
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The optimization of direct dìgital frequency synthesizer performance in the presence of finite word length effects
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H. T. Nicholas, H. Samueli, and B. Kim, "The optimization of direct dìgital frequency synthesizer performance in the presence of finite word length effects," in Proc. 42nd Annu. Frequency Control Symp., 1988, pp. 357-363.
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Nicholas, H.T.1
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0021479005
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CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communications
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Aug.
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D. A. Sunderland, R. A. Strauch, S. S. Wharfield, H. T. Peterson. and C. R. Cole, "CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communications," IEEE J. Solid-State Circuits, vol. SC-19, pp. 497-505, Aug. 1984.
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Sunderland, D.A.1
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9
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84865904164
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"High resolution phase to sine amplitude conversion," U.S. Patent 4905 177, Feb. 27, 1990
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L. A. Weaver and R. J. Kerr, "High resolution phase to sine amplitude conversion," U.S. Patent 4905 177, Feb. 27, 1990.
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Weaver, L.A.1
Kerr, R.J.2
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54549123452
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A 540 MHz 10b polar-to-Cartesian converter
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Feb.
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G. Gielis, R. van de Plassche, and J. van Valburg, "A 540 MHz 10b polar-to-Cartesian converter," in ISSCC Dig. Tech. Papers, Feb. 1991, pp. 160-161.
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Gielis, G.1
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11
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0024121927
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1.25 GHz 26-bit pipelined digital accumulator
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Nov.
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J. Chow, F. F. Lee, P. M. Lau, C. G. Ekroot, and J. E. Hornung, "1.25 GHz 26-bit pipelined digital accumulator," in 1988 GaAs IC Symp. Tech. Dig., Nov. 1988, pp. 131-134.
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Chow, J.1
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12
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0030415312
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Spur reduction techniques in sine output direct digital synthesis
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June
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J. Vankka, "Spur reduction techniques in sine output direct digital synthesis," in Proc. 1996 IEEE Frequency Control Symp., June 1996, pp. 951-959.
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(1996)
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Vankka, J.1
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13
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0029182058
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A high performance modular embedded ROM architecture
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May
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M. Duhalde and A. Greiner, "A high performance modular embedded ROM architecture," in Proc. ISCAS, May 1995, pp. 1057-1060.
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Duhalde, M.1
Greiner, A.2
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14
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0015722690
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A monolithic 10-b digital-to-analog converter using ion implantation
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Dec.
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G. Kelson, H. Stellrecht, and D. Perloff, "A monolithic 10-b digital-to-analog converter using ion implantation," IEEE J. Solid-State Circuits, vol. 8, pp. 396-403, Dec. 1973.
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Kelson, G.1
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0027576336
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Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits
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Apr.
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D. K. Su, M. J. Loinaz, S. Masui, and B. A. H. Wooley, "Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits," IEEE J. Solid-State Circuits, vol. 28, pp. 420-429, Apr. 1993.
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Su, D.K.1
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Masui, S.3
Wooley, B.A.H.4
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16
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0026190361
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A 10-b 40-MHz 0.8-μm CMOS current-output D/A-converter
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July
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C. A. A. Bastiaansen, D. W. J. Groeneveld, H. J. Schouwenaars, and H. A. H. Termeer, "A 10-b 40-MHz 0.8-μm CMOS current-output D/A-converter," IEEE J. Solid-State Circuits, vol. 26, pp. 917-921, July 1991.
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Bastiaansen, C.A.A.1
Groeneveld, D.W.J.2
Schouwenaars, H.J.3
Termeer, H.A.H.4
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