Low-power design of decimation filters for a digital IF receiver

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 3, 2000, Pages 339-345

  White, Brian A ^a   Elmasry, Mohamed I ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

DELTA SIGMA MODULATION; DIGITAL FILTERS; DIGITAL SIGNAL PROCESSING; ELECTRIC POWER FACTOR; ELECTRIC POWER SUPPLIES TO APPARATUS; FREQUENCIES; SAMPLING; SIGNAL RECEIVERS; VLSI CIRCUITS; WIRELESS TELECOMMUNICATION SYSTEMS;

DECIMATION FILTERS; MOBITEX AND ARDIS NETWORK; MULTIMODE DECIMATION FILTER; SINGLE MODE TWO STAGE DESIGN;

ELECTRIC NETWORK SYNTHESIS;

EID: 0033722284     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.845900     Document Type: Article

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