DNL and INL yield models for a current-steering D/A converter

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2003, Pages

  Kosunen, Marko ^a   Vankka, Jouko ^a   Teikari, Ilari ^a   Halonen, Kari ^a  

^a AALTO UNIVERSITY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; MATHEMATICAL MODELS; REGRESSION ANALYSIS;

CURRENT-STEERING;

DIGITAL TO ANALOG CONVERSION;

EID: 0038489128     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Y. Cong, R. L. Geiger, "Formulation of INL and DNL Yield Estimation in Current-Steering D/A Converters", Proc. of IEEE ISCAS 2002, Phoenix, USA, Vol. III, pp. 149-152.
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3. J. Bastos, A. M. Marques, M. S. J. Steyaert, W. Sansen, "A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC", IEEE JSSC, Vol. 33, No. 12, Dec. 1998, pp. 1959-1969.
4. K. R. Lakshmikumar, R. A. Hadaway, M. A. Copeland, "Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design", IEEE JSSC, Vol. sc-21, No. 6, Dec. 1986, pp. 1057-1066.
5. K. R. Lakshmikumar, M. A. Copeland, R. A. Hadaway, "Reply to 'A comment on "Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design"", IEEE JSSC, Vol, 23, No. 1, Feb 1988, pp. 296.
6. A. Van den Bosch, M. Steyaert, W. Sansen, "An Accurate Statistical Yield Model for CMOS Current-Steering D/A Converters", in Proc. of IEEE ISCAS 2000, Geneva, Switzerland, Vol. IV, pp. 105-108.