A new hardware-efficient architecture for programmable FIR filters

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 43, Issue 9, 1996, Pages 637-644

  Lee, Hwan Rei ^b   Jen, Chein Wei ^a,b   Liu, Chi Min ^b  

^a IEEE

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CALCULATIONS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; SIGNAL ENCODING; SIGNAL FILTERING AND PREDICTION;

MODIFIED BOOTH MULTIPLIER; MULTIPLICATION COMPLEXITY; PROGRAMMABLE FILTERS;

DIGITAL FILTERS;

EID: 0030243321     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.536760     Document Type: Article

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