A 1.5V 14b 100MS/s self-calibrated DAC

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Cong, Yonghua ^a   Geiger, Randall L ^a  

^a Iowa State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS;

GATE SOURCE VOLTAGES; LEAST SIGNIFICANT BITS; MOST SIGNIFICANT BITS;

DIGITAL CIRCUITS;

EID: 0037630997     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. 2 Random Walk CMOS DAC," IEEE J. Solid-State Circuits, vol. 34, pp. 1708-1718. Dec. 1999.
2. A. Bugeja et al., "A Self-Trimming 14-b 100MS/s CMOS DAC," IEEE J. Solid-State Circuits, vol. 35, pp. 1841-1852, Dec. 2000.
3. D. Groeneveld, et al., "A Self-Calibration Technique for Monolithic High-Resolution D/A Converters," IEEE J. Solid-state Circuits, vol. 24, pp. 1517-1522, Dec. 1989.
4. 2 CMOS DAC," IEEE J. Solid-state Circuits, vol. 36, pp. 1144-1147, July 2001.