ROM size reduction with low processing cost for Direct Digital Frequency Synthesis

IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings

Volumn I, Issue , 2001, Pages 287-290

  Langlois, J M P ^a   Al Khalili, D ^a  

^a ROYAL MILITARY COLLEGE OF CANADA   (Canada)

Author keywords

Direct digital frequency synthesis (DDFS); Direct digital synthesis (DDS); Table look up synthesis

Indexed keywords

COMPUTATIONAL COMPLEXITY; FREQUENCY SYNTHESIZERS; ROM; TABLE LOOKUP;

DIRECT DIGITAL FREQUENCY SYNTHESIS (DDFS);

DIRECT DIGITAL CONTROL SYSTEMS;

EID: 0034770262     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. A digital frequency synthesizer
2. Spurious signals in direct digital frequency synthesizers due to the phase truncation
3. A low-power CMOS digitally synthesized 0-13 MHz agile sinewave generator
4. A 2-V, 2-GHz low-power direct digital frequency synthesizer chip-set for wireless communication
5. Low-power direct digital frequency synthesis for wireless communications
6. CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communications
7. The optimization of direct digital frequency synthesizer performance in the presence of finite word length effects
8. Mapping from phase to sine-amplitude in direct digital frequency synthesizers using parabolic approximation
9. Methods of mapping from phase to sine amplitude in direct digital synthesis