An 800-MHz 1-μm CMOS pipelined 8-b adder using true single-phase clocked logic-flip-flops

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 3, 1996, Pages 401-409

  Rogenmoser, Robert ^a,b,c,d   Huang, Qiuting ^a,b,c,e,f,g  

^a IEEE

^b ETH ZURICH   (Switzerland)

^c SWISS FEDERAL INSTITUTE OF TECHNOLOGY   (Switzerland)

^d ETH ^*

^e HARBIN INSTITUTE OF TECHNOLOGY   (China)

^f UNIVERSITY OF LEUVEN   (Belgium)

^g UNIVERSITY OF EAST ANGLIA   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CARRY LOGIC; ELECTRIC NETWORK SYNTHESIS; ELECTRIC POWER UTILIZATION; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; LOGIC GATES;

CARRY INCREMENT ADDERS; CLOCK DISTRIBUTION; COMBINATORIAL GATES; FINE GRAIN PIPELINE TECHNIQUE; TRUE SINGLE PHASE CLOCKING;

ADDERS;

EID: 0030110217     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.494202     Document Type: Article

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