-
1
-
-
0016116644
-
Design of ion-implanted MOSFETs with very small physical dimensions
-
Oct
-
R. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, and A. LeBlanc, "Design of ion-implanted MOSFETs with very small physical dimensions," IEEE J. Solid-State Circuits, vol. SSC-9, no. 5, pp. 256-268, Oct. 1974.
-
(1974)
IEEE J. Solid-State Circuits
, vol.SSC-9
, Issue.5
, pp. 256-268
-
-
Dennard, R.1
Gaensslen, F.H.2
Rideout, V.L.3
Bassous, E.4
LeBlanc, A.5
-
2
-
-
0021406605
-
Generalized scaling theory and its application to a 1/4 micrometer MOSFET design
-
Apr
-
G. Baccarani, M. R. Wordeman, and R. Dennard, "Generalized scaling theory and its application to a 1/4 micrometer MOSFET design," IEEE Trans. Electron Devices, vol. ED-31, no. 4, pp. 452-462, Apr. 1984.
-
(1984)
IEEE Trans. Electron Devices
, vol.ED-31
, Issue.4
, pp. 452-462
-
-
Baccarani, G.1
Wordeman, M.R.2
Dennard, R.3
-
4
-
-
0042912833
-
Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs
-
Sep
-
A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva, "Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1837-1852, Sep. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.9
, pp. 1837-1852
-
-
Asenov, A.1
Brown, A.R.2
Davies, J.H.3
Kaya, S.4
Slavcheva, G.5
-
5
-
-
0036507826
-
Maintaining the benefits of CMOS scaling when scaling bogs down
-
E. J. Nowak, "Maintaining the benefits of CMOS scaling when scaling bogs down," IBM J. Res. Develop., vol. 46, no. 2/3, pp. 169-180, 2002.
-
(2002)
IBM J. Res. Develop
, vol.46
, Issue.2-3
, pp. 169-180
-
-
Nowak, E.J.1
-
6
-
-
0033362679
-
Technology and design challenges for low power and high performance
-
V. De and S. Borkar, "Technology and design challenges for low power and high performance," in Proc. ISLPED, 1999, pp. 163-168.
-
(1999)
Proc. ISLPED
, pp. 163-168
-
-
De, V.1
Borkar, S.2
-
7
-
-
33748582367
-
Silicon CMOS devices beyond scaling
-
Jul
-
W. Haensch, E. J. Nowak, R. H. Dennard, P. M. Solomon, A. Bryant, O. H. Dokumaci, A. Kumar, X. Wang, J. B. Johnson, and M. V. Fischetti, "Silicon CMOS devices beyond scaling," IBM J. Res. Develop., vol. 50, no. 4/5, pp. 339-361, Jul. 2006.
-
(2006)
IBM J. Res. Develop
, vol.50
, Issue.4-5
, pp. 339-361
-
-
Haensch, W.1
Nowak, E.J.2
Dennard, R.H.3
Solomon, P.M.4
Bryant, A.5
Dokumaci, O.H.6
Kumar, A.7
Wang, X.8
Johnson, J.B.9
Fischetti, M.V.10
-
8
-
-
33748614600
-
Advanced high-k dielectric stacks with polySi and metal gates: Recent progress and current challenges
-
Jul
-
E. P. Gusev, V. Narayanan, and M. M. Frank, "Advanced high-k dielectric stacks with polySi and metal gates: Recent progress and current challenges," IBM J. Res. Develop., vol. 50, no. 4/5, pp. 387-410, Jul. 2006.
-
(2006)
IBM J. Res. Develop
, vol.50
, Issue.4-5
, pp. 387-410
-
-
Gusev, E.P.1
Narayanan, V.2
Frank, M.M.3
-
9
-
-
33847749489
-
Channel backscattering characteristics of strained PMOSFETs with embedded SiGe source/drain
-
H.-N. Lin, H.-W. Chen, C.-H. Ko, C.-H. Ge, H.-C. Lin, T.-Y. Huang, and W.-C. Lee, "Channel backscattering characteristics of strained PMOSFETs with embedded SiGe source/drain," in IEDM Tech. Dig., 2005, pp. 141-144.
-
(2005)
IEDM Tech. Dig
, pp. 141-144
-
-
Lin, H.-N.1
Chen, H.-W.2
Ko, C.-H.3
Ge, C.-H.4
Lin, H.-C.5
Huang, T.-Y.6
Lee, W.-C.7
-
10
-
-
11144354892
-
A logic nanotechnology featuring strained-silicon
-
Apr
-
S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, M. Zhiyong, B. Mcintyre, A. Murthy, B. Obradovic, L. Shiften, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, "A logic nanotechnology featuring strained-silicon," IEEE Electron Device Lett., vol. 25, no. 4, pp. 191-193, Apr. 2004.
-
(2004)
IEEE Electron Device Lett
, vol.25
, Issue.4
, pp. 191-193
-
-
Thompson, S.E.1
Armstrong, M.2
Auth, C.3
Cea, S.4
Chau, R.5
Glass, G.6
Hoffman, T.7
Klaus, J.8
Zhiyong, M.9
Mcintyre, B.10
Murthy, A.11
Obradovic, B.12
Shiften, L.13
Sivakumar, S.14
Tyagi, S.15
Ghani, T.16
Mistry, K.17
Bohr, M.18
El-Mansy, Y.19
-
11
-
-
0026896303
-
Scaling the Si MOSFET: From bulk to SOI to bulk
-
Jul
-
R.-H. Yan et al., "Scaling the Si MOSFET: From bulk to SOI to bulk," IEEE Trans. Electron Devices, vol. 39, no. 7, pp. 1704-1710, Jul. 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, Issue.7
, pp. 1704-1710
-
-
Yan, R.-H.1
-
12
-
-
0027847411
-
Scaling theory for double-gate SOI MOSFETs
-
Dec
-
K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, "Scaling theory for double-gate SOI MOSFETs," IEEE Trans. Electron Devices vol. 40, no. 12, pp. 2326-2329, Dec. 1993.
-
(1993)
IEEE Trans. Electron Devices
, vol.40
, Issue.12
, pp. 2326-2329
-
-
Suzuki, K.1
Tanaka, T.2
Tosaka, Y.3
Horie, H.4
Arimoto, Y.5
-
13
-
-
0031998367
-
Temperature dependent thermal conductivity of single-crystal silicon layers in SOI substrates
-
M. Asheghi, M. N. Touzelbaev, K. E. Goodson, Y. K. Leung, and S. S. Wong, "Temperature dependent thermal conductivity of single-crystal silicon layers in SOI substrates," Trans. ASME, J. Heat Transf., vol. 120, no. 1, pp. 30-36, 1998.
-
(1998)
Trans. ASME, J. Heat Transf
, vol.120
, Issue.1
, pp. 30-36
-
-
Asheghi, M.1
Touzelbaev, M.N.2
Goodson, K.E.3
Leung, Y.K.4
Wong, S.S.5
-
14
-
-
0001246055
-
Phonon scattering in silicon films with thickness of order 100 nm
-
May
-
Y. S. Ju and K. E. Goodson, "Phonon scattering in silicon films with thickness of order 100 nm," Appl. Phys. Lett., vol. 74, no. 20, pp. 3005-3007, May 1999.
-
(1999)
Appl. Phys. Lett
, vol.74
, Issue.20
, pp. 3005-3007
-
-
Ju, Y.S.1
Goodson, K.E.2
-
15
-
-
29744465652
-
Thermal conductivity measurements of ultrathin single crystal silicon layers
-
Jan
-
W. Liu and M. Asheghi, "Thermal conductivity measurements of ultrathin single crystal silicon layers," Trans. ASME, J. Heat Transf., vol. 128, no. 1, pp. 75-83, Jan. 2006.
-
(2006)
Trans. ASME, J. Heat Transf
, vol.128
, Issue.1
, pp. 75-83
-
-
Liu, W.1
Asheghi, M.2
-
16
-
-
33746629889
-
Modeling and data for thermal conductivity of ultrathin single-crystal SOI layers at high temperature
-
Aug
-
W. Liu, K. Etessam-Yazdani, R. Hussin, and M. Asheghi, "Modeling and data for thermal conductivity of ultrathin single-crystal SOI layers at high temperature," IEEE Trans. Electron Devices, vol. 53, no. 8, pp. 1868-1876, Aug. 2006.
-
(2006)
IEEE Trans. Electron Devices
, vol.53
, Issue.8
, pp. 1868-1876
-
-
Liu, W.1
Etessam-Yazdani, K.2
Hussin, R.3
Asheghi, M.4
-
17
-
-
84944378006
-
Measurement and modeling of self-heating in SOI nMOSFETs
-
Jan
-
L. T. Su, J. E. Chung, D. A. Antoniadis, K. E. Goodson, and M. I. Flik, "Measurement and modeling of self-heating in SOI nMOSFETs," IEEE Trans. Electron Devices, vol. 41, no. 1, pp. 69-75, Jan. 1994.
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, Issue.1
, pp. 69-75
-
-
Su, L.T.1
Chung, J.E.2
Antoniadis, D.A.3
Goodson, K.E.4
Flik, M.I.5
-
18
-
-
0029255981
-
An AC conductance technique for measuring self-heating in SOI MOSFETs
-
Feb
-
R. H. Tu, C. Wann, J. C. King, P. K. Ko, and C. Hu, "An AC conductance technique for measuring self-heating in SOI MOSFETs," IEEE Electron Device Lett., vol. 16, no. 2, pp. 67-69, Feb. 1995.
-
(1995)
IEEE Electron Device Lett
, vol.16
, Issue.2
, pp. 67-69
-
-
Tu, R.H.1
Wann, C.2
King, J.C.3
Ko, P.K.4
Hu, C.5
-
19
-
-
0029291056
-
Measurement of I-V curves of silicon-on-insulator (SOI) MOSFET's without self-heating
-
Apr
-
K. A. Jenkins and J. Y.-C. Sun, "Measurement of I-V curves of silicon-on-insulator (SOI) MOSFET's without self-heating," IEEE Electron Device Lett., vol. 16, no. 4, pp. 145-147, Apr. 1995.
-
(1995)
IEEE Electron Device Lett
, vol.16
, Issue.4
, pp. 145-147
-
-
Jenkins, K.A.1
Sun, J.Y.-C.2
-
20
-
-
0030379801
-
Self-heating effects in SOI MOSFET's and their measurement by small signal conductance techniques
-
Dec
-
B. M. Tenbroek, M. S. L. Lee, W. Redman-White, R. J. T. Bunyan, and M. J. Uren, "Self-heating effects in SOI MOSFET's and their measurement by small signal conductance techniques," IEEE Trans. Electron Devices vol. 43, no. 12, pp. 2240-2248, Dec. 1996.
-
(1996)
IEEE Trans. Electron Devices
, vol.43
, Issue.12
, pp. 2240-2248
-
-
Tenbroek, B.M.1
Lee, M.S.L.2
Redman-White, W.3
Bunyan, R.J.T.4
Uren, M.J.5
-
21
-
-
0842309721
-
Thermal analysis of ultra-thin body device scaling
-
E. Pop, R. Dutton, and K. Goodson, "Thermal analysis of ultra-thin body device scaling," in IEDM Tech. Dig., 2003, pp. 883-884.
-
(2003)
IEDM Tech. Dig
, pp. 883-884
-
-
Pop, E.1
Dutton, R.2
Goodson, K.3
-
22
-
-
21644480747
-
Electrothermal comparison and performance optimization of thin-body SOI and GOI MOSFETs
-
E. Pop, C. O. Chui, S. Sinha, R. Dutton, and K. Goodson, "Electrothermal comparison and performance optimization of thin-body SOI and GOI MOSFETs," in IEDM Tech. Dig., 2004, pp. 411-414.
-
(2004)
IEDM Tech. Dig
, pp. 411-414
-
-
Pop, E.1
Chui, C.O.2
Sinha, S.3
Dutton, R.4
Goodson, K.5
-
23
-
-
0026137501
-
Estimation of heat transfer in SOI-MOSFETs
-
Apr
-
M. Berger and Z. Chai, "Estimation of heat transfer in SOI-MOSFETs," IEEE Trans. Electron Devices, vol. 38, no. 4, pp. 871-875, Apr. 1991.
-
(1991)
IEEE Trans. Electron Devices
, vol.38
, Issue.4
, pp. 871-875
-
-
Berger, M.1
Chai, Z.2
-
24
-
-
0029274172
-
Scaling constraints imposed by self-heating in submicron SOI MOSFET's
-
Mar
-
D. A. Dallmann and K. Shenai, "Scaling constraints imposed by self-heating in submicron SOI MOSFET's," IEEE Trans. Electron Devices, vol. 42, no. 3, pp. 489-496, Mar. 1996.
-
(1996)
IEEE Trans. Electron Devices
, vol.42
, Issue.3
, pp. 489-496
-
-
Dallmann, D.A.1
Shenai, K.2
-
25
-
-
33645832552
-
Impact of self-heating effect on long-term reliability and performance degradation in CMOS circuits
-
Mar
-
O. Semenov, A. Vassighi, and M. Sachdev, "Impact of self-heating effect on long-term reliability and performance degradation in CMOS circuits," IEEE Trans. Device Mater. Rel., vol. 6, no. 1, pp. 17-27, Mar. 2006.
-
(2006)
IEEE Trans. Device Mater. Rel
, vol.6
, Issue.1
, pp. 17-27
-
-
Semenov, O.1
Vassighi, A.2
Sachdev, M.3
-
26
-
-
33845695095
-
Joule heating under quasi-ballistic transport conditions in bulk and strained silicon devices
-
E. Pop, J. Rowlette, R. W. Dutton, and K. E. Goodson, "Joule heating under quasi-ballistic transport conditions in bulk and strained silicon devices," in Proc. Int. Conf. SISPAD, 2005, pp. 307-310.
-
(2005)
Proc. Int. Conf. SISPAD
, pp. 307-310
-
-
Pop, E.1
Rowlette, J.2
Dutton, R.W.3
Goodson, K.E.4
-
27
-
-
46049111245
-
Self-consistent and efficient electrothermal analysis for poly/metal gate FinFETs
-
Dec
-
S. Kumar, R. V. Joshi, C.-T. Chuang, K. Kim, J. Y. Murthy, K. T. Schonenberg, and E. J. Nowak, "Self-consistent and efficient electrothermal analysis for poly/metal gate FinFETs," in IEDM Tech. Dig., Dec. 2006, pp. 803-806.
-
(2006)
IEDM Tech. Dig
, pp. 803-806
-
-
Kumar, S.1
Joshi, R.V.2
Chuang, C.-T.3
Kim, K.4
Murthy, J.Y.5
Schonenberg, K.T.6
Nowak, E.J.7
-
28
-
-
0025512595
-
Rigorous thermodynamic treatment of heat generation and conduction in semiconductor device modeling
-
Nov
-
G. K. Wachutka, "Rigorous thermodynamic treatment of heat generation and conduction in semiconductor device modeling," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 9, no. 11, pp. 1141-1149, Nov. 1990.
-
(1990)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst
, vol.9
, Issue.11
, pp. 1141-1149
-
-
Wachutka, G.K.1
-
29
-
-
0037439322
-
Nanoscale thermal transport
-
Jan
-
D. G. Cahill, W. K. Ford, K. E. Goodson, G. D. Mahan, A. Majumdar, H. J. Maris, R. Merlin, and S. R. Phillpot, "Nanoscale thermal transport," J. Appl. Phys., vol. 93, no. 2, pp. 793-818, Jan. 2003.
-
(2003)
J. Appl. Phys
, vol.93
, Issue.2
, pp. 793-818
-
-
Cahill, D.G.1
Ford, W.K.2
Goodson, K.E.3
Mahan, G.D.4
Majumdar, A.5
Maris, H.J.6
Merlin, R.7
Phillpot, S.R.8
-
30
-
-
33745047441
-
Review: Multiscale thermal modeling in nanoelectronics
-
S. Sinha and K. E. Goodson, "Review: Multiscale thermal modeling in nanoelectronics," Int. J. Multiscale Comput. Eng., vol. 3, no. 1, pp. 107-133, 2005.
-
(2005)
Int. J. Multiscale Comput. Eng
, vol.3
, Issue.1
, pp. 107-133
-
-
Sinha, S.1
Goodson, K.E.2
-
31
-
-
33845912527
-
A split-flux model for phonon transport near hotspots
-
Anaheim, CA, Nov. 13-20
-
S. Sinha, E. Pop, and K. E. Goodson, "A split-flux model for phonon transport near hotspots," in Proc. IMECE-61949, Anaheim, CA, Nov. 13-20, 2004.
-
(2004)
Proc. IMECE-61949
-
-
Sinha, S.1
Pop, E.2
Goodson, K.E.3
-
32
-
-
33751438797
-
Thermal simulation techniques for nanoscale transistors
-
J. Rowlette, E. Pop, S. Sinha, M. Panzer, and K. Goodson, "Thermal simulation techniques for nanoscale transistors," in Proc. ICCAD, 2005, pp. 225-228.
-
(2005)
Proc. ICCAD
, pp. 225-228
-
-
Rowlette, J.1
Pop, E.2
Sinha, S.3
Panzer, M.4
Goodson, K.5
-
33
-
-
29244435059
-
Understanding quasi-ballistic transport in nano-MOSFETs: Part I - Scattering in the channel and in the drain
-
Dec
-
P. Palestri, D. Esseni, S. Eminente, C. Fiegna, E. Sangiorgi, and L. Selmi, "Understanding quasi-ballistic transport in nano-MOSFETs: Part I - Scattering in the channel and in the drain," IEEE Trans. Electron Devices, vol. 52, no. 12, pp. 2727-2735, Dec. 2005.
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, Issue.12
, pp. 2727-2735
-
-
Palestri, P.1
Esseni, D.2
Eminente, S.3
Fiegna, C.4
Sangiorgi, E.5
Selmi, L.6
-
34
-
-
29244485621
-
Understanding quasi-ballistic transport in nano-MOSFETS: Part II - Technology scaling along the ITRS
-
Dec
-
S. Eminente, D. Esseni, P. Palestri, C. Fiegna, L. Selmi, and E. Sangiorgi, "Understanding quasi-ballistic transport in nano-MOSFETS: Part II - Technology scaling along the ITRS," IEEE Trans. Electron Devices, vol. 52, no. 12, pp. 2736-2743, Dec. 2005.
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, Issue.12
, pp. 2736-2743
-
-
Eminente, S.1
Esseni, D.2
Palestri, P.3
Fiegna, C.4
Selmi, L.5
Sangiorgi, E.6
-
35
-
-
0031191310
-
Elementary scattering theory of the Si MOSFET
-
Jul
-
M. Lundstrom, "Elementary scattering theory of the Si MOSFET," IEEE Electron Device Lett., vol. 18, no. 7, pp. 361-363, Jul. 1997.
-
(1997)
IEEE Electron Device Lett
, vol.18
, Issue.7
, pp. 361-363
-
-
Lundstrom, M.1
-
36
-
-
0036253371
-
Essential physics of carrier transport in nanoscale MOSFETs
-
Jan
-
M. Lundstrom and Z. Ren, "Essential physics of carrier transport in nanoscale MOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 133-141, Jan. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.1
, pp. 133-141
-
-
Lundstrom, M.1
Ren, Z.2
-
37
-
-
0036930453
-
Temperature dependent channel backscattering coefficients in nanoscale MOSFETs
-
M.-J. Chen, H.-T. Huang, K.-C. Huang, P.-N. Chen, C.-S. Chang, and C. H. Diaz, "Temperature dependent channel backscattering coefficients in nanoscale MOSFETs," in IEDM Tech. Dig., 2002, pp. 39-42.
-
(2002)
IEDM Tech. Dig
, pp. 39-42
-
-
Chen, M.-J.1
Huang, H.-T.2
Huang, K.-C.3
Chen, P.-N.4
Chang, C.-S.5
Diaz, C.H.6
-
38
-
-
37749001321
-
Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits
-
Nov
-
J. H. Choi, A. Bansal, M. Meterelliyoz, J. Murthy, and K. Roy, "Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits," in Proc. ICCAD, Nov. 2006, pp. 583-586.
-
(2006)
Proc. ICCAD
, pp. 583-586
-
-
Choi, J.H.1
Bansal, A.2
Meterelliyoz, M.3
Murthy, J.4
Roy, K.5
-
40
-
-
0035696689
-
Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application
-
Dec
-
D. Esseni, M. Mastrapasqua, G. K. Celler, C. Fiegna, L. Selmi, and E. Sangiorgi, "Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application," IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2842-2850, Dec. 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, Issue.12
, pp. 2842-2850
-
-
Esseni, D.1
Mastrapasqua, M.2
Celler, G.K.3
Fiegna, C.4
Selmi, L.5
Sangiorgi, E.6
-
42
-
-
0033712947
-
MOSFET Modeling into the ballistic regime
-
J. D. Bude, "MOSFET Modeling into the ballistic regime," in Proc. Int. Conf. SISPAD, 2000, pp. 23-26.
-
(2000)
Proc. Int. Conf. SISPAD
, pp. 23-26
-
-
Bude, J.D.1
-
43
-
-
32044450519
-
Simulation of nanoscale MOSFETs using modified drift-diffusion and hydrodynamic models and comparison with Monte Carlo results
-
Feb
-
R. Granzner, V. M. Polyakov, F. Schwierz, M. Kittler, R. J. Luyken, W. Rosner, and M. Stadele, "Simulation of nanoscale MOSFETs using modified drift-diffusion and hydrodynamic models and comparison with Monte Carlo results," Microelectron. Eng., vol. 83, no. 2, pp. 241-246, Feb. 2006.
-
(2006)
Microelectron. Eng
, vol.83
, Issue.2
, pp. 241-246
-
-
Granzner, R.1
Polyakov, V.M.2
Schwierz, F.3
Kittler, M.4
Luyken, R.J.5
Rosner, W.6
Stadele, M.7
-
44
-
-
14844291284
-
Carrier quantization in SOI MOSFETs using an effective potential based Monte-Carlo tool
-
P. Palestri, D. Esseni, A. Abramo, R. Clerc, and L. Selmi, "Carrier quantization in SOI MOSFETs using an effective potential based Monte-Carlo tool," in Proc. Eur. Solid-State Device Res. Conf., 2003, pp. 407-410.
-
(2003)
Proc. Eur. Solid-State Device Res. Conf
, pp. 407-410
-
-
Palestri, P.1
Esseni, D.2
Abramo, A.3
Clerc, R.4
Selmi, L.5
-
45
-
-
0034453530
-
Quantum effects in MOSFETs: Use of an effective potential in 3D Monte Carlo simulation of ultra-short channel devices
-
D. K. Ferry, R. Akis, and D. Vasileska, "Quantum effects in MOSFETs: Use of an effective potential in 3D Monte Carlo simulation of ultra-short channel devices," in IEDM Tech. Dig., 2000, pp. 287-290.
-
(2000)
IEDM Tech. Dig
, pp. 287-290
-
-
Ferry, D.K.1
Akis, R.2
Vasileska, D.3
-
46
-
-
14844303532
-
An improved semi-classical Monte-Carlo approach for nanoscale MOSFET simulation
-
May
-
P. Palestri, S. Eminente, D. Esseni, C. Fiegna, E. Sangiorgi, and L. Selmi, "An improved semi-classical Monte-Carlo approach for nanoscale MOSFET simulation," Solid State Electron., vol. 49, no. 5, pp. 727-732, May 2005.
-
(2005)
Solid State Electron
, vol.49
, Issue.5
, pp. 727-732
-
-
Palestri, P.1
Eminente, S.2
Esseni, D.3
Fiegna, C.4
Sangiorgi, E.5
Selmi, L.6
-
47
-
-
0028747841
-
On the universality of inversion-layer mobility in Si MOSFETs: Part I - Effects of substrate impurity concentration
-
Dec
-
S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion-layer mobility in Si MOSFETs: Part I - Effects of substrate impurity concentration," IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2357-2362, Dec. 1994.
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, Issue.12
, pp. 2357-2362
-
-
Takagi, S.1
Toriumi, A.2
Iwase, M.3
Tango, H.4
-
48
-
-
84957871180
-
Monte-Carlo simulation of decananometric double-gate SOI devices: Multi-subband vs. 3D-electron gas with quantum corrections
-
P. Riolino, M. Braccioli, L. Lucci, D. Esseni, C. Fiegna, P. Palestri, and L. Selmi, "Monte-Carlo simulation of decananometric double-gate SOI devices: Multi-subband vs. 3D-electron gas with quantum corrections," in Proc. ESSDERC, 2006, pp. 162-165.
-
(2006)
Proc. ESSDERC
, pp. 162-165
-
-
Riolino, P.1
Braccioli, M.2
Lucci, L.3
Esseni, D.4
Fiegna, C.5
Palestri, P.6
Selmi, L.7
-
49
-
-
0016576617
-
Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature
-
Nov
-
C. Canali et al., "Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature," IEEE Trans. Electron Devices, vol. ED-22, no. 11, pp. 1045-1047, Nov. 1975.
-
(1975)
IEEE Trans. Electron Devices
, vol.ED-22
, Issue.11
, pp. 1045-1047
-
-
Canali, C.1
-
50
-
-
0037870335
-
An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode
-
Mar
-
D. Esseni, M. Mastrapasqua, G. K. Celler, C. Fiegna, L. Selmi, and E. Sangiorgi, "An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode," IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 802-808, Mar. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.3
, pp. 802-808
-
-
Esseni, D.1
Mastrapasqua, M.2
Celler, G.K.3
Fiegna, C.4
Selmi, L.5
Sangiorgi, E.6
-
51
-
-
84939377322
-
Effect of microscale thermal conduction on the packing limit of silicon-on-insulator electronic devices
-
Oct
-
K. E. Goodson and M. I. Flik, "Effect of microscale thermal conduction on the packing limit of silicon-on-insulator electronic devices," IEEE Trans. Compon., Hybrids, Manuf. Technol., vol. 15, no. 5, pp. 715-722, Oct. 1992.
-
(1992)
IEEE Trans. Compon., Hybrids, Manuf. Technol
, vol.15
, Issue.5
, pp. 715-722
-
-
Goodson, K.E.1
Flik, M.I.2
-
52
-
-
0036160813
-
Analytical thermal model for multilevel VLSI interconnects incorporating via effect
-
Jan
-
T.-Y. Chiang, K. Banerjee, and K. C. Saraswat, "Analytical thermal model for multilevel VLSI interconnects incorporating via effect," IEEE Electron Device Lett., vol. 23, no. 1, pp. 31-33, Jan. 2002.
-
(2002)
IEEE Electron Device Lett
, vol.23
, Issue.1
, pp. 31-33
-
-
Chiang, T.-Y.1
Banerjee, K.2
Saraswat, K.C.3
-
53
-
-
79955997863
-
Measurement of thermal conductivity of buried oxides of silicon-on-insulator wafers fabricated by separation by implantation of oxygen technology
-
Sep
-
P. He et al., "Measurement of thermal conductivity of buried oxides of silicon-on-insulator wafers fabricated by separation by implantation of oxygen technology," Appl. Phys. Lett., vol. 81, no. 10, pp. 1896-1898, Sep. 2002.
-
(2002)
Appl. Phys. Lett
, vol.81
, Issue.10
, pp. 1896-1898
-
-
He, P.1
-
54
-
-
0037097910
-
Measurement of thermal conductivity of silicon dioxide thin films using a 3ω method
-
Jun
-
T. Yamane et al., "Measurement of thermal conductivity of silicon dioxide thin films using a 3ω method," J. Appl. Phys., vol. 91, no. 12, pp. 9772-9776, Jun. 2002.
-
(2002)
J. Appl. Phys
, vol.91
, Issue.12
, pp. 9772-9776
-
-
Yamane, T.1
-
55
-
-
0142217023
-
Impact of self-heating on digital SOI an strained-silicon CMOS circuits
-
K. A. Jenkins and R. L. Franch, "Impact of self-heating on digital SOI an strained-silicon CMOS circuits," in Proc. SOI Conf., 2003, pp. 161-163.
-
(2003)
Proc. SOI Conf
, pp. 161-163
-
-
Jenkins, K.A.1
Franch, R.L.2
-
56
-
-
0034225988
-
The influence of elevated temperature on degradation and lifetime prediction of thin silicon-dioxide films
-
Jul
-
B. Kaczer, R. Degraeve, N. Pangon, and G. Groeseneken, "The influence of elevated temperature on degradation and lifetime prediction of thin silicon-dioxide films," IEEE Trans. Electron Devices, vol. 47, no. 7, pp. 1514-1521, Jul. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.7
, pp. 1514-1521
-
-
Kaczer, B.1
Degraeve, R.2
Pangon, N.3
Groeseneken, G.4
-
57
-
-
0031334714
-
Measurement and simulation of self-heating in SOI CMOS analogue circuits
-
B. M. Tenbroek, M. S. L. Lee, W. Redman-White, C. F. Edwards, R. J. T. Bunyan, and M. J. Uren, "Measurement and simulation of self-heating in SOI CMOS analogue circuits," in Proc. IEEE Int. SOI Conf., 1997, pp. 156-157.
-
(1997)
Proc. IEEE Int. SOI Conf
, pp. 156-157
-
-
Tenbroek, B.M.1
Lee, M.S.L.2
Redman-White, W.3
Edwards, C.F.4
Bunyan, R.J.T.5
Uren, M.J.6
-
58
-
-
37749040412
-
Quantifying self-heating effects in strained Si MOSFETs with scaling
-
R. Agaiby, A. O'Neill, S. Olsen, G. Eneman, P. Verheyen, R. Loo, and C. Claeys, "Quantifying self-heating effects in strained Si MOSFETs with scaling," in Proc. ESSDERC, 2006, pp. 97-100.
-
(2006)
Proc. ESSDERC
, pp. 97-100
-
-
Agaiby, R.1
O'Neill, A.2
Olsen, S.3
Eneman, G.4
Verheyen, P.5
Loo, R.6
Claeys, C.7
-
59
-
-
84907705533
-
Substrate effects on the small-signal characteristics of SOI MOSFETs
-
Florence, Italy, Sep
-
V. Kilchytska, D. Levacq, D. Lederer, J.-P. Raskin, and D. Flandre, "Substrate effects on the small-signal characteristics of SOI MOSFETs," in Proc. ESSDERC, Florence, Italy, Sep. 2002, pp. 519-522.
-
(2002)
Proc. ESSDERC
, pp. 519-522
-
-
Kilchytska, V.1
Levacq, D.2
Lederer, D.3
Raskin, J.-P.4
Flandre, D.5
-
60
-
-
0042592899
-
Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs
-
Jun
-
V. Kilchytska, D. Levacq, D. Lederer, J.-P. Raskin, and D. Flandre, "Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs," IEEE Electron Device Lett., vol. 24, no. 6, pp. 414-416, Jun. 2003.
-
(2003)
IEEE Electron Device Lett
, vol.24
, Issue.6
, pp. 414-416
-
-
Kilchytska, V.1
Levacq, D.2
Lederer, D.3
Raskin, J.-P.4
Flandre, D.5
|