Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2006, Pages 583-586

  Choi, Jung Hwan ^a   Bansal, Aditya ^a   Meterelliyoz, Mesut ^a   Murthy, Jayathi ^a   Roy, Kaushik ^a  

^a Purdue University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DESIGN; ELECTRIC NETWORK ANALYSIS; FIELD EFFECT TRANSISTORS; HEALTH; LOGIC DEVICES; MOBILE TELECOMMUNICATION SYSTEMS;

(I ,J) CONDITIONS; CIRCUIT BLOCKS; COMPUTER-AIDED DESIGN; INTERNATIONAL CONFERENCES; LEAKAGE POWER; LOGIC CELLS; MOSFETS; ROOM-TEMPERATURE (RT); SUB THRESHOLD LEAKAGE; TEMPERATURE ESTIMATIONS; TEMPERATURE MAPS; TRADE OFFS;

NETWORKS (CIRCUITS);

EID: 37749001321     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320104     Document Type: Conference Paper

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